diff options
| -rw-r--r-- | src/mainboard/hp/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/Kconfig | 104 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/bootblock.c | 48 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/chip.h | 26 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/cmos.layout | 98 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/devicetree.cb | 90 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 145 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/irq_tables.c | 51 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/mainboard.c | 34 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h | 44 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/mptable.c | 192 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/romstage.c | 242 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/spd_addr.h | 111 | ||||
| -rw-r--r-- | src/superio/serverengines/pilot/pilot_early_init.c | 29 |
14 files changed, 1214 insertions, 3 deletions
diff --git a/src/mainboard/hp/Kconfig b/src/mainboard/hp/Kconfig index 19de4243c1..9f59ec8e90 100644 --- a/src/mainboard/hp/Kconfig +++ b/src/mainboard/hp/Kconfig @@ -7,6 +7,8 @@ config BOARD_HP_DL145_G1 bool "ProLiant DL145 G1" config BOARD_HP_DL145_G3 bool "ProLiant DL145 G3" +config BOARD_HP_DL165_G6_FAM10 + bool "ProLiant DL165 G6 Fam10" config BOARD_HP_E_VECTRA_P2706T bool "e-Vectra P2706T" @@ -14,6 +16,7 @@ endchoice source "src/mainboard/hp/dl145_g1/Kconfig" source "src/mainboard/hp/dl145_g3/Kconfig" +source "src/mainboard/hp/dl165_g6_fam10/Kconfig" source "src/mainboard/hp/e_vectra_p2706t/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig new file mode 100644 index 0000000000..7052f5bc8e --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -0,0 +1,104 @@ +if BOARD_HP_DL165_G6_FAM10 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_F_1207 + select NORTHBRIDGE_AMD_AMDFAM10 + select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + select SOUTHBRIDGE_BROADCOM_BCM21000 + select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_NSC_PC87417 + select HAVE_OPTION_TABLE + select HAVE_BUS_CONFIG + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select CACHE_AS_RAM + select HAVE_HARD_RESET + select LIFT_BSP_APIC_ID + select BOARD_ROMSIZE_KB_1024 + select ENABLE_APIC_EXT_ID + select AMDMCT + select TINY_BOOTBLOCK + +config MAINBOARD_DIR + string + default hp/dl165_g6_fam10 + +config DCACHE_RAM_BASE + hex + default 0xc4000 + +config DCACHE_RAM_SIZE + hex + default 0x0c000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x04000 + +config APIC_ID_OFFSET + hex + default 0 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + +config MAINBOARD_PART_NUMBER + string + default "ProLiant DL165 G6 (Fam10)" + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config MAX_CPUS + int + default 12 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x6 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + +config IRQ_SLOT_COUNT + int + default 15 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + +config RAMBASE + hex + default 0x200000 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "mainboard/hp/dl165_g6_fam10/bootblock.c" + +config MMCONF_SUPPORT_DEFAULT + bool + default y + +endif # BOARD_HP_DL165_G6_FAM10 diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c new file mode 100644 index 0000000000..2c56c4ccf5 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -0,0 +1,48 @@ +#include <device/pnp_def.h> + +#define SCH4307_CONFIG_PORT 0x162e +static inline void shc4307_enter_ext_func_mode(device_t dev) +{ + unsigned port = dev >> 8; + outb(0x55, port); +} + +static inline void shc4307_exit_ext_func_mode(device_t dev) +{ + unsigned port = dev >> 8; + outb(0xaa, port); +} + +#define CMOS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x6) +#define KBD_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x7) +#define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) +#define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) + +void shc4307_init(void) +{ + shc4307_enter_ext_func_mode(CMOS_DEV); + pnp_set_logical_device(CMOS_DEV); /* CMOS/RTC */ + pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70); + pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72); + pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8); + /* pnp_set_enable(CMOS_DEV, 3); */ + pnp_write_config(CMOS_DEV, 0x30, 3); + + pnp_set_logical_device(KBD_DEV); /* Keyboard */ + pnp_set_irq(KBD_DEV, PNP_IDX_IRQ0, 1); + pnp_set_enable(KBD_DEV, 1); + + pnp_set_logical_device(DBG_DEV); /* Debug */ + pnp_set_iobase(DBG_DEV, PNP_IDX_IO0, 0x80); + pnp_set_enable(DBG_DEV, 1); + + pnp_set_logical_device(REGS_DEV); + pnp_set_iobase(REGS_DEV, PNP_IDX_IO0, 0x600); + pnp_set_enable(REGS_DEV, 1); + + shc4307_exit_ext_func_mode(CMOS_DEV); +} + +static void bootblock_southbridge_init(void) { + shc4307_init(); +} diff --git a/src/mainboard/hp/dl165_g6_fam10/chip.h b/src/mainboard/hp/dl165_g6_fam10/chip.h new file mode 100644 index 0000000000..6c54f71126 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config { +}; + diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout new file mode 100644 index 0000000000..1c6a3cde86 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb new file mode 100644 index 0000000000..3c1302b5aa --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb @@ -0,0 +1,90 @@ +chip northbridge/amd/amdfam10/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_F_1207 + device lapic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 # northbridge + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # devices on link 2 + chip southbridge/broadcom/bcm21000 # HT2100 + device pci 0.0 on + end # bridge to slot PCI-E 4x ?? + device pci 1.0 on + end + device pci 2.0 on + end # unused + device pci 3.0 on # bridge to slot PCI-E 16x ?? + end + device pci 4.0 on + end # unused + device pci 5.0 on + device pci 4.0 on end # BCM5715 NIC + device pci 4.1 on end # BCM5715 NIC + end + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PCI/PCI-X bridge 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on end # Legacy pci main 0x0205 + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.3 off # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.4 off end # SWC + device pnp 4e.5 off end # Mouse + device pnp 4e.6 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.7 off end # GPIO + device pnp 4e.f off end # XBUS + device pnp 4e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end # end superio + end # end pci 1.2 + device pci 1.3 off end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 3.0 on end # VGA + end + end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # amdfam10 + + end #pci_domain +end + + diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c new file mode 100644 index 0000000000..f275841e70 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu@amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/multicore.h> +#endif + +#include <cpu/amd/amdfam10_sysconf.h> + +#include <stdlib.h> +#include "mb_sysconf.h" + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +struct mb_sysconf_t mb_sysconf; + +/* Here you only need to set value in pci1234 for HT-IO that could be + installed or not You may need to preset pci1234 for HTIO board, please + refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +static u32 pci1234x[] = { + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, +}; + + +/* HT Chain device num, actually it is unit id base of every ht device + in chain, assume every chain only have 4 ht device at most */ + +static unsigned hcdnx[] = { + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, +}; + +extern void get_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + + unsigned apicid_base; + + device_t dev; + int i; + struct mb_sysconf_t *m; + + if(get_bus_conf_done==1) return; //do it only once + + get_bus_conf_done = 1; + + sysconf.mb = &mb_sysconf; + + m = sysconf.mb; + memset(m, 0, sizeof(struct mb_sysconf_t)); + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + + for(i=0;i<sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 + + m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 12) & 0xff; + m->bus_bcm5780[0] = m->bus_bcm5785_0; + + /* bcm5785 */ + printk(BIOS_DEBUG, "search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0); + dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0)); + if (dev) { + printk(BIOS_DEBUG, "found dev %s...\n",dev_path(dev)); + m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1); + dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); + printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev)); + if(dev) { + m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; + printk(BIOS_DEBUG, "bus_isa 1=%d\n",m->bus_isa); +#endif + } + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn); + } + + /* bcm5780 */ + for(i = 1; i < 6; i++) { + dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); + if(dev) { + m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; + printk(BIOS_DEBUG, "bus_isa 2=%d\n",m->bus_isa); +#endif + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1); + } + } + +/*I/O APICs: APIC ID Version State Address*/ + apicid_base = 0x10; + for(i=0;i<3;i++) + m->apicid_bcm5785[i] = apicid_base+i; +} diff --git a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c b/src/mainboard/hp/dl165_g6_fam10/irq_tables.c new file mode 100644 index 0000000000..eb629e045a --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/irq_tables.c @@ -0,0 +1,51 @@ +/* This file was generated by getpir.c, do not modify! + * (but if you do, please run checkpir on it to verify) + * + * Contains the IRQ Routing Table dumped directly from your + * memory, which BIOS sets up. + * + * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx + */ + +#ifdef GETPIR +#include "pirq_routing.h" +#else +#include <arch/pirq_routing.h> +#endif + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 11, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x02 << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1166, /* Vendor */ + 0x36, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xe9, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x01, (0x0e << 3) | 0x0, {{0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}}, 0x0, 0x0}, /* 1166:024a */ + {0x00, (0x03 << 3) | 0x0, {{0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}}, 0x0, 0x0}, /* 1166:0223 */ + {0x00, (0x06 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x0, 0x0}, /* 1166:0140 */ + {0x00, (0x07 << 3) | 0x0, {{0x23, 0xdac0}, {0x23, 0xdac0}, {0x23, 0xdac0}, {0x23, 0xdac0}}, 0x0, 0x0}, /* 1166:0142 */ + {0x00, (0x08 << 3) | 0x0, {{0x22, 0xdac0}, {0x22, 0xdac0}, {0x22, 0xdac0}, {0x22, 0xdac0}}, 0x0, 0x0}, /* 1166:0144 */ + {0x00, (0x09 << 3) | 0x0, {{0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}}, 0x0, 0x0}, /* 1166:0142 */ + {0x00, (0x0a << 3) | 0x0, {{0x20, 0xdac0}, {0x20, 0xdac0}, {0x20, 0xdac0}, {0x20, 0xdac0}}, 0x0, 0x0}, /* 1166:0144 */ + {0x02, (0x02 << 3) | 0x0, {{0x28, 0xdac0}, {0x27, 0xdac0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* 14e4:1648 */ + {0x06, (0x00 << 3) | 0x0, {{0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}}, 0x2, 0x0}, + {0x03, (0x00 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x2, 0x0}, + {0x07, (0x00 << 3) | 0x0, {{0x2a, 0xdac0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* 102b:0522 */ + } +}; + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/hp/dl165_g6_fam10/mainboard.c b/src/mainboard/hp/dl165_g6_fam10/mainboard.c new file mode 100644 index 0000000000..1a4cf1c0b6 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for Uni of Mannheim. + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("HP DL165 G6 Mainboard (Family 10)") +}; diff --git a/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h b/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h new file mode 100644 index 0000000000..de965c7004 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu@gmail.com> for AMD. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MB_SYSCONF_H +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_isa; + unsigned char bus_bcm5780[7]; + unsigned char bus_bcm5785_0; + unsigned char bus_bcm5785_1; + unsigned char bus_bcm5785_1_1; + unsigned apicid_bcm5785[3]; + + unsigned sbdn2; + unsigned bus_type[256]; +}; + +#endif + diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c new file mode 100644 index 0000000000..f1e5f40874 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com> + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu@gmail.com> for AMD. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/io.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/multicore.h> +#endif + +#include <cpu/amd/amdfam10_sysconf.h> + +#include "mb_sysconf.h" + +static void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "HP DL165 G6 "; + struct mp_config_table *mc; + int isa_bus; + + struct mb_sysconf_t *m; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + m = sysconf.mb; + + mptable_write_buses(mc, NULL, &isa_bus); + printk(BIOS_DEBUG, "writing %d as ISA to mptable (%d for real)...\n", isa_bus, m->bus_isa); + + /*I/O APICs: APIC ID Version State Address*/ + { + device_t dev = 0; + int i; + struct resource *res; + for(i=0; i<3; i++) { + dev = dev_find_device(0x1166, 0x0235, dev); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base); + smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); + } + } + } + + } + + /* IRQ routing as factory BIOS */ + outb(0x00, 0xc00); outb(0x09, 0xc01); + outb(0x01, 0xc00); outb(0x0a, 0xc01); + outb(0x02, 0xc00); outb(0x0e, 0xc01); + outb(0x03, 0xc00); outb(0x07, 0xc01); + outb(0x07, 0xc00); outb(0x05, 0xc01); + + // 8259 registers... + outb(0xa0, 0x4d0); + outb(0x0e, 0x4d1); + + { + device_t dev; + dev = dev_find_device(0x1166, 0x0205, 0); + if(dev) { + uint32_t dword; + dword = pci_read_config32(dev, 0x64); + dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 + pci_write_config32(dev, 0x64, dword); + } + // set GEVENT pins to NO OP + /* outb(0x33, 0xcd6); outb(0x00, 0xcd7); + outb(0x34, 0xcd6); outb(0x00, 0xcd7); + outb(0x35, 0xcd6); outb(0x00, 0xcd7); */ + } + + // hide XIOAPIC PCI configuration space + { + device_t dev; + dev = dev_find_device(0x1166, 0x205, 0); + if (dev) { + uint32_t dword; + dword = pci_read_config32(dev, 0x64); + dword |= (1<<26); + pci_write_config32(dev, 0x64, dword); + } + } + + mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0); + + /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0, m->apicid_bcm5785[0], 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0, m->apicid_bcm5785[0], 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0, m->apicid_bcm5785[2], 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1, m->apicid_bcm5785[2], 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0, m->apicid_bcm5785[2], 0xa); + + /* enable int */ + /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ + { + device_t dev; + dev = dev_find_device(0x1166, 0x0205, 0); + if(dev) { + uint32_t dword; + dword = pci_read_config32(dev, 0x6c); + dword |= (1<<4); // enable interrupts + printk(BIOS_DEBUG, "6ch: %x\n",dword); + pci_write_config32(dev, 0x6c, dword); + } + } + + /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + + //extended table entries + smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); + smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); + smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); + smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0); + smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f); + smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006); + smp_write_bus_hierarchy(mc, 8, 0x01, 0); + smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); + smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); + + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c new file mode 100644 index 0000000000..0e0347d8c8 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Tyan + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define RAMINIT_SYSINFO 1 + +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 1 + +#define QRANK_DIMM_SUPPORT 1 + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif + +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 + +#define DBGP_DEFAULT 7 + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include <console/console.h> +#include "lib/ramtest.c" +#include <cpu/amd/model_10xxx_rev.h> +#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "northbridge/amd/amdfam10/raminit.h" +#include "northbridge/amd/amdfam10/amdfam10.h" + +#include "cpu/amd/model_10xxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdfam10/reset_test.c" + +#include "superio/serverengines/pilot/pilot_early_serial.c" +#include "superio/serverengines/pilot/pilot_early_init.c" +#include "superio/nsc/pc87417/pc87417_early_serial.c" + +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdfam10/debug.c" + +#include "cpu/x86/mtrr/earlymtrr.c" + +//#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) +#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) + +#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + u8 val; + outb(0x3d, 0x0cd6); + outb(0x87, 0x0cd7); + + outb(0x44, 0xcd6); + val = inb(0xcd7); + outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdfam10/amdfam10.h" + +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/amdfam10_pci.c" + +#include "cpu/amd/quadcore/quadcore.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" +#include "cpu/amd/model_10xxx/init_cpus.c" + +#include "northbridge/amd/amdfam10/early_ht.c" + +#include "spd_addr.h" + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + + u32 bsp_apicid = 0; + u32 val; + msr_t msr; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + /* mov bsp to bus 0xff when > 8 nodes */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + bcm5785_enable_rom(); + bcm5785_enable_lpc(); + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + + post_code(0x30); + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + + pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + uart_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + console_init(); + pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + post_code(0x33); + + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fixup prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ + + wait_all_core0_started(); + +#if CONFIG_LOGICAL_CPUS==1 + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); +#endif + +#if SET_FIDVID == 1 + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + + /* FIXME: The sb fid change may survive the warm reset and only + * need to be done once.*/ + + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); +#endif + + init_timer(); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + /* It's the time to set ctrl in sysinfo now; */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + enable_smbus(); + + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID + + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + + bcm5785_early_setup(); + + post_cache_as_ram(); +} diff --git a/src/mainboard/hp/dl165_g6_fam10/spd_addr.h b/src/mainboard/hp/dl165_g6_fam10/spd_addr.h new file mode 100644 index 0000000000..6a201c7e61 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/spd_addr.h @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * This file defines the SPD addresses for the mainboard. Must be included in + * romstage.c + */ + +#define RC00 0 +#define RC01 1 +#define RC02 2 +#define RC03 3 +#define RC04 4 +#define RC05 5 +#define RC06 6 +#define RC07 7 +#define RC08 8 +#define RC09 9 +#define RC10 10 +#define RC11 11 +#define RC12 12 +#define RC13 13 +#define RC14 14 +#define RC15 15 +#define RC16 16 +#define RC17 17 +#define RC18 18 +#define RC19 19 +#define RC20 20 +#define RC21 21 +#define RC22 22 +#define RC23 23 +#define RC24 24 +#define RC25 25 +#define RC26 26 +#define RC27 27 +#define RC28 28 +#define RC29 29 +#define RC30 30 +#define RC31 31 + +#define RC32 32 +#define RC33 33 +#define RC34 34 +#define RC35 35 +#define RC36 36 +#define RC37 37 +#define RC38 38 +#define RC39 39 +#define RC40 40 +#define RC41 41 +#define RC42 42 +#define RC43 43 +#define RC44 44 +#define RC45 45 +#define RC46 46 +#define RC47 47 +#define RC48 48 +#define RC49 49 +#define RC50 50 +#define RC51 51 +#define RC52 52 +#define RC53 53 +#define RC54 54 +#define RC55 55 +#define RC56 56 +#define RC57 57 +#define RC58 58 +#define RC59 59 +#define RC60 60 +#define RC61 61 +#define RC62 62 +#define RC63 63 + + +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 +#define DIMM4 0x54 +#define DIMM5 0x55 +#define DIMM6 0x56 +#define DIMM7 0x57 + + +static const u8 spd_addr[] = { + // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +}; + diff --git a/src/superio/serverengines/pilot/pilot_early_init.c b/src/superio/serverengines/pilot/pilot_early_init.c index 08aa5a7624..f5444ac4f5 100644 --- a/src/superio/serverengines/pilot/pilot_early_init.c +++ b/src/superio/serverengines/pilot/pilot_early_init.c @@ -37,6 +37,16 @@ static void pilot_early_init(device_t dev) pilot_disable_serial(PNP_DEV(port, 0x1)); print_debug("disable serial 1\n"); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x3)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0x0b00); + pnp_set_iobase(dev, 0x62, 0x0b80); + pnp_set_iobase(dev, 0x64, 0x0b84); + pnp_set_iobase(dev, 0x66, 0x0b86); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + /* pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3)); @@ -58,14 +68,27 @@ static void pilot_early_init(device_t dev) pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x5), 0); pnp_exit_ext_func_mode(dev); -/* + pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x6)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + pnp_set_irq(dev, PNP_IDX_IRQ0, 1); + pnp_set_drq(dev, 0x71, 3); + pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port, 0x6), 0); + pnp_set_logical_device(PNP_DEV(port, 0xe)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x70); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x72); + pnp_set_irq(dev, PNP_IDX_IRQ0, 8); + pnp_set_drq(dev, 0x71, 3); + pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); -*/ + pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x7)); pnp_exit_ext_func_mode(dev); |