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-rw-r--r--src/soc/intel/skylake/cpu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 3ec8d2c702..e8616f08c4 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -197,7 +197,7 @@ static void configure_thermal_target(void)
config_t *conf = dev->chip_info;
msr_t msr;
- /* Set TCC activaiton offset if supported */
+ /* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
msr = rdmsr(MSR_TEMPERATURE_TARGET);
@@ -366,9 +366,6 @@ static void cpu_core_init(device_t cpu)
/* Configure Intel Speed Shift */
configure_isst();
- /* Thermal throttle activation offset */
- configure_thermal_target();
-
/* Enable Direct Cache Access */
configure_dca_cap();
@@ -484,6 +481,9 @@ void soc_init_cpus(device_t dev)
if (mp_init_with_smm(cpu_bus, &mp_ops)) {
printk(BIOS_ERR, "MP initialization failure.\n");
}
+
+ /* Thermal throttle activation offset */
+ configure_thermal_target();
}
int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)