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-rw-r--r--src/mainboard/google/hatch/ramstage.c3
-rw-r--r--src/mainboard/google/sarien/ramstage.c14
2 files changed, 4 insertions, 13 deletions
diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c
index b8e80e744a..5824e66735 100644
--- a/src/mainboard/google/hatch/ramstage.c
+++ b/src/mainboard/google/hatch/ramstage.c
@@ -16,6 +16,7 @@
#include <arch/acpi.h>
#include <baseboard/variants.h>
#include <ec/ec.h>
+#include <soc/gpio.h>
#include <soc/ramstage.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -26,7 +27,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
size_t num_gpios;
gpio_table = variant_gpio_table(&num_gpios);
- gpio_configure_pads(gpio_table, num_gpios);
+ cnl_configure_pads(gpio_table, num_gpios);
}
static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index c2dc27daee..96321f8d49 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -14,6 +14,7 @@
*/
#include <arch/acpi.h>
+#include <soc/gpio.h>
#include <soc/ramstage.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -24,22 +25,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
size_t num_gpios;
gpio_table = variant_gpio_table(&num_gpios);
- gpio_configure_pads(gpio_table, num_gpios);
-}
-
-/* Workaround FSP issue by reprogramming GPIOs after FSP-S */
-static void mainboard_init(struct device *dev)
-{
- const struct pad_config *gpio_table;
- size_t num_gpios;
-
- gpio_table = variant_gpio_table(&num_gpios);
- gpio_configure_pads(gpio_table, num_gpios);
+ cnl_configure_pads(gpio_table, num_gpios);
}
static void mainboard_enable(struct device *dev)
{
- dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}