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-rw-r--r--src/devices/pci_device.c3
-rw-r--r--src/mainboard/tyan/s2880/Config.lb22
-rw-r--r--src/mainboard/tyan/s2880/auto.c8
-rw-r--r--src/mainboard/tyan/s2882/Config.lb23
-rw-r--r--src/mainboard/tyan/s2882/auto.c8
-rw-r--r--src/mainboard/tyan/s2882/mptable.c4
-rw-r--r--src/mainboard/tyan/s2885/Config.lb30
-rw-r--r--src/mainboard/tyan/s2885/auto.c5
-rw-r--r--src/mainboard/tyan/s2885/resourcemap.c2
-rw-r--r--src/mainboard/via/epia/auto.c4
-rw-r--r--targets/tyan/s2880/Config.lb22
-rw-r--r--targets/tyan/s2882/Config.lb2
-rw-r--r--targets/tyan/s2885/Config.lb13
-rw-r--r--targets/via/epia/Config.filo.lb109
-rw-r--r--targets/via/epia/Config.lb7
15 files changed, 198 insertions, 64 deletions
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index ffa420739a..734b982a6d 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -699,6 +699,8 @@ static void pci_level_irq(unsigned char intNum)
outb((unsigned char) intBits, 0x4d0);
outb((unsigned char) (intBits >> 8), 0x4d1);
+ /* this seems like an error but is not ... */
+#if 0
if (inb(0x4d0) != (intBits & 0xf)) {
printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
__FUNCTION__, intBits &0xf, inb(0x4d0));
@@ -707,6 +709,7 @@ static void pci_level_irq(unsigned char intNum)
printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
__FUNCTION__, (intBits>>8) &0xf, inb(0x4d1));
}
+#endif
}
/*
diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb
index d05f4e6967..87f54b925b 100644
--- a/src/mainboard/tyan/s2880/Config.lb
+++ b/src/mainboard/tyan/s2880/Config.lb
@@ -142,20 +142,24 @@ northbridge amd/amdk8 "mc0"
pci 0:18.1
pci 0:18.2
pci 0:18.3
- southbridge amd/amd8131 "amd8131"
+ southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
- southbridge amd/amd8111 "amd8111"
+ southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
- pci 0:1.0
- pci 0:1.1
- pci 0:1.2
- pci 0:1.3
- pci 0:1.5
- pci 0:1.6
+ pci 0:1.0 on
+ pci 0:1.1 on
+ pci 0:1.2 on
+ pci 0:1.3 on
+ pci 0:1.5 off
+ pci 0:1.6 off
+ pci 1:0.0 on
+ pci 1:0.1 on
+ pci 1:0.2 on
+ pci 1:1.0 off
end
end
@@ -182,7 +186,7 @@ end
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
-dir /bioscall
+#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c
index 07bcc1d92f..b5135d1a5c 100644
--- a/src/mainboard/tyan/s2880/auto.c
+++ b/src/mainboard/tyan/s2880/auto.c
@@ -15,6 +15,8 @@
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
+#include "northbridge/amd/amdk8/cpu_rev.c"
+
#define REV_B_RESET 0
static void memreset_setup(void)
@@ -88,8 +90,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
-#include "northbridge/amd/amdk8/cpu_ldtstop.c"
-#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
+//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
+//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@@ -162,7 +164,7 @@ static void main(void)
enable_lapic();
init_timer();
if (!boot_cpu() ) {
- notify_bsp_ap_is_stopped();
+// notify_bsp_ap_is_stopped();
stop_this_cpu();
}
uart_init();
diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb
index 9c9fc016b5..7f06909c66 100644
--- a/src/mainboard/tyan/s2882/Config.lb
+++ b/src/mainboard/tyan/s2882/Config.lb
@@ -13,6 +13,7 @@ uses ARCH
###
### Build the objects we have code for in this directory.
###
+##object mainboard.o
config chip.h
register "fixup_scsi" = "1"
register "fixup_vga" = "1"
@@ -140,20 +141,24 @@ northbridge amd/amdk8 "mc0"
pci 0:18.1
pci 0:18.2
pci 0:18.3
- southbridge amd/amd8131 "amd8131"
+ southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
- southbridge amd/amd8111 "amd8111"
+ southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
- pci 0:1.0
- pci 0:1.1
- pci 0:1.2
- pci 0:1.3
- pci 0:1.5
- pci 0:1.6
+ pci 0:1.0 on
+ pci 0:1.1 on
+ pci 0:1.2 on
+ pci 0:1.3 on
+ pci 0:1.5 off
+ pci 0:1.6 off
+ pci 1:0.0 on
+ pci 1:0.1 on
+ pci 1:0.2 on
+ pci 1:1.0 off
end
end
@@ -179,7 +184,7 @@ end
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
-dir /bioscall
+#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
diff --git a/src/mainboard/tyan/s2882/auto.c b/src/mainboard/tyan/s2882/auto.c
index 2de3c2f5c4..cbd54c348c 100644
--- a/src/mainboard/tyan/s2882/auto.c
+++ b/src/mainboard/tyan/s2882/auto.c
@@ -15,6 +15,8 @@
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
+#include "northbridge/amd/amdk8/cpu_rev.c"
+
static void memreset_setup(void)
{
@@ -84,8 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
-#include "northbridge/amd/amdk8/cpu_ldtstop.c"
-#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
+//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
+//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@@ -182,7 +184,7 @@ static void main(void)
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
-#if 1
+#if 0
dump_pci_devices();
#endif
#if 0
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 01cabe127c..6f1ce50602 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -88,7 +88,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
#endif
//Onboard SI Serial ATA
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, 0x2, 0x11);
-#if 0
+#if 1
//Slot 3 PCIX 100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x21, 0x3, 0x0);
@@ -107,7 +107,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
//On Board NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x24, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x25, 0x3, 0x1);
-#if 0
+#if 1
//Slot 1 PCI-X 133/100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xc, 0x4, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xd, 0x4, 0x1);
diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index a234b03841..ba172926b2 100644
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -13,6 +13,7 @@ uses ARCH
###
### Build the objects we have code for in this directory.
###
+##object mainboard.o
config chip.h
register "fixup_scsi" = "1"
register "fixup_vga" = "1"
@@ -141,24 +142,29 @@ northbridge amd/amdk8 "mc0"
pci 0:18.1
pci 0:18.2
pci 0:18.3
- southbridge amd/amd8131 "amd8131"
+ southbridge amd/amd8131 "amd8131" link 2
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
- southbridge amd/amd8111 "amd8111"
+ southbridge amd/amd8111 "amd8111" link 2
pci 0:0.0
- pci 0:1.0
- pci 0:1.1
- pci 0:1.2
- pci 0:1.3
- pci 0:1.5
- pci 0:1.6
+ pci 0:1.0 on
+ pci 0:1.1 on
+ pci 0:1.2 on
+ pci 0:1.3 on
+ pci 0:1.5 on
+ pci 0:1.6 off
+ pci 1:0.0 on
+ pci 1:0.1 on
+ pci 1:0.2 on
+ pci 1:1.0 off
+
end
- southbridge amd/amd8151 "amd8151"
- pci 2:0.0
- pci 2:1.0
+ southbridge amd/amd8151 "amd8151" link 0
+ pci 0:0.0
+ pci 0:1.0
end
end
@@ -187,7 +193,7 @@ end
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
-dir /bioscall
+#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c
index 30e3c22097..4d8ba2176b 100644
--- a/src/mainboard/tyan/s2885/auto.c
+++ b/src/mainboard/tyan/s2885/auto.c
@@ -16,6 +16,8 @@
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
+#include "northbridge/amd/amdk8/cpu_rev.c"
+
#define REV_B_RESET 0
static void memreset_setup(void)
@@ -89,9 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
-#include "northbridge/amd/amdk8/cpu_ldtstop.c"
-#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
diff --git a/src/mainboard/tyan/s2885/resourcemap.c b/src/mainboard/tyan/s2885/resourcemap.c
index db5957ec07..f2535bf02f 100644
--- a/src/mainboard/tyan/s2885/resourcemap.c
+++ b/src/mainboard/tyan/s2885/resourcemap.c
@@ -254,6 +254,8 @@ static void setup_s2885_resource_map(void)
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000203,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050003,
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x00000203,
+// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c
index fa83d5c3c1..4b6632d196 100644
--- a/src/mainboard/via/epia/auto.c
+++ b/src/mainboard/via/epia/auto.c
@@ -26,8 +26,8 @@ void udelay(int usecs)
#include "southbridge/via/vt8231/vt8231_early_smbus.c"
-#define MAXIMUM_CONSOLE_LOGLEVEL 9
-#define DEFAULT_CONSOLE_LOGLEVEL 9
+#define MAXIMUM_CONSOLE_LOGLEVEL 6
+#define DEFAULT_CONSOLE_LOGLEVEL 6
#include "southbridge/via/vt8231/vt8231_early_serial.c"
static void memreset_setup(void)
diff --git a/targets/tyan/s2880/Config.lb b/targets/tyan/s2880/Config.lb
index 1892b25368..e9183a0f54 100644
--- a/targets/tyan/s2880/Config.lb
+++ b/targets/tyan/s2880/Config.lb
@@ -56,11 +56,11 @@ uses XIP_ROM_BASE
uses HAVE_HARD_RESET
-uses CONFIG_VGABIOS
-uses CONFIG_REALMODE_IDT
-uses CONFIG_PCIBIOS
-uses VGABIOS_START
-uses SCSIFW_START
+#uses CONFIG_VGABIOS
+#uses CONFIG_REALMODE_IDT
+#uses CONFIG_PCIBIOS
+#uses VGABIOS_START
+#uses SCSIFW_START
#
#uses CONFIG_LSI_SCSI_FW_FIXUP
@@ -78,11 +78,11 @@ option k7=1
option k8=1
option ROM_SIZE=524288
-option CONFIG_VGABIOS=0
-option CONFIG_REALMODE_IDT=0
-option CONFIG_PCIBIOS=0
-option VGABIOS_START=0xfff8c000
-option SCSIFW_START=0xfff80000
+#option CONFIG_VGABIOS=0
+#option CONFIG_REALMODE_IDT=0
+#option CONFIG_PCIBIOS=0
+#option VGABIOS_START=0xfff8c000
+#option SCSIFW_START=0xfff80000
option HAVE_FALLBACK_BOOT=1
@@ -236,4 +236,4 @@ romimage "fallback"
payload ../../tg3.zelf
end
-buildrom ROM_SIZE "normal" "fallback"
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2882/Config.lb b/targets/tyan/s2882/Config.lb
index 5d4287d914..dae08d7363 100644
--- a/targets/tyan/s2882/Config.lb
+++ b/targets/tyan/s2882/Config.lb
@@ -235,4 +235,4 @@ romimage "fallback"
payload ../../tg3.zelf
end
-buildrom ROM_SIZE "normal" "fallback"
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2885/Config.lb b/targets/tyan/s2885/Config.lb
index 3f2258f818..67828b9126 100644
--- a/targets/tyan/s2885/Config.lb
+++ b/targets/tyan/s2885/Config.lb
@@ -41,7 +41,6 @@ uses USE_FALLBACK_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses CONFIG_CHIP_CONFIGURE
-uses CONFIG_LEGACY_VGABIOS
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
@@ -56,10 +55,10 @@ uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_HARD_RESET
-uses CONFIG_VGABIOS
-uses CONFIG_REALMODE_IDT
-uses CONFIG_PCIBIOS
-uses VGABIOS_START
+#uses CONFIG_VGABIOS
+#uses CONFIG_REALMODE_IDT
+#uses CONFIG_PCIBIOS
+#uses VGABIOS_START
#uses SCSIFW_START
#
@@ -76,7 +75,7 @@ option k7=1
option k8=1
option ROM_SIZE=524288
-option CONFIG_LEGACY_VGABIOS=1
+#option CONFIG_VGABIOS=1
#option CONFIG_REALMODE_IDT=1
#option CONFIG_PCIBIOS=1
#option VGABIOS_START=1
@@ -235,4 +234,4 @@ romimage "fallback"
payload ../../tg3--ide_disk.zelf
end
-buildrom ROM_SIZE "normal" "fallback"
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia/Config.filo.lb b/targets/via/epia/Config.filo.lb
new file mode 100644
index 0000000000..9349303821
--- /dev/null
+++ b/targets/via/epia/Config.filo.lb
@@ -0,0 +1,109 @@
+# Sample config file for Motorola Sandpoint X3 Demo Board with
+# the Arima HDAMA
+# This will make a target directory of ./hdama
+
+loadoptions
+
+target epia
+
+uses ARCH
+uses CONFIG_COMPRESS
+uses CONFIG_IOAPIC
+uses CONFIG_KEYBOARD
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_UDELAY_TSC
+uses CPU_FIXUP
+uses FALLBACK_SIZE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_HARD_RESET
+uses i586
+uses i686
+uses INTEL_PPRO_MTRR
+uses HEAP_SIZE
+uses IRQ_SLOT_COUNT
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses CONFIG_SMP
+uses CONFIG_MAX_CPUS
+uses MEMORY_HOLE
+uses PAYLOAD_SIZE
+uses _RAMBASE
+uses _ROMBASE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_OFFSET
+uses ROM_SECTION_SIZE
+uses ROM_SIZE
+uses STACK_SIZE
+uses USE_FALLBACK_IMAGE
+uses USE_OPTION_TABLE
+uses HAVE_OPTION_TABLE
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses MAINBOARD
+uses CONFIG_CHIP_CONFIGURE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses LINUXBIOS_EXTRA_VERSION
+
+option CONFIG_CHIP_CONFIGURE=1
+option CONFIG_KEYBOARD=1
+
+option MAXIMUM_CONSOLE_LOGLEVEL=10
+option DEFAULT_CONSOLE_LOGLEVEL=10
+option CONFIG_CONSOLE_SERIAL8250=1
+
+option CPU_FIXUP=1
+option CONFIG_UDELAY_TSC=0
+option i686=1
+option i586=1
+option INTEL_PPRO_MTRR=1
+option ROM_SIZE=256*1024
+
+option HAVE_OPTION_TABLE=1
+option CONFIG_ROM_STREAM=1
+option HAVE_FALLBACK_BOOT=1
+
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+option FALLBACK_SIZE=131072
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x00004000
+
+#
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+
+#
+# Arima hdama
+romimage "normal"
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ mainboard via/epia
+# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
+# payload ../../../../tg3--ide_disk.zelf
+# payload ../../../../../lnxieepro100.ebi
+ payload ../../../../../../filo.elf
+end
+
+romimage "fallback"
+ option USE_FALLBACK_IMAGE=1
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ mainboard via/epia
+# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
+# payload ../../../../tg3--ide_disk.zelf
+# payload ../../../../../lnxieepro100.ebi
+ payload ../../../../../../filo.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb
index 192fef2690..c0e111e534 100644
--- a/targets/via/epia/Config.lb
+++ b/targets/via/epia/Config.lb
@@ -48,12 +48,15 @@ uses CONFIG_CHIP_CONFIGURE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses LINUXBIOS_EXTRA_VERSION
+uses TTYS0_BAUD
+
+option TTYS0_BAUD=19200
option CONFIG_CHIP_CONFIGURE=1
option CONFIG_KEYBOARD=1
-option MAXIMUM_CONSOLE_LOGLEVEL=10
-option DEFAULT_CONSOLE_LOGLEVEL=10
+option MAXIMUM_CONSOLE_LOGLEVEL=7
+option DEFAULT_CONSOLE_LOGLEVEL=7
option CONFIG_CONSOLE_SERIAL8250=1
option CPU_FIXUP=1
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-30 19:25:49 +0000