diff options
| -rw-r--r-- | src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c | 4 | ||||
| -rw-r--r-- | src/southbridge/via/vt8237r/vt8237r_lpc.c | 7 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c index c34597201b..0a0a9f2d08 100644 --- a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c @@ -309,6 +309,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif init_timer(); ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c index 4af73af263..5d2579e530 100644 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c @@ -222,6 +222,13 @@ void setup_pm(device_t dev) /* SCI is generated for RTC/pwrBtn/slpBtn. */ outw(0x001, VT8237R_ACPI_IO_BASE + 0x04); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); } static void vt8237r_init(struct device *dev) |