diff options
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/mainboard.c | 28 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 47 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 6 |
3 files changed, 28 insertions, 53 deletions
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index cc32b998ec..d0d6c6bdbe 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */ +#include <string.h> #include <types.h> #include <device/device.h> +#include <device/pci_def.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> #include <pc80/mc146818rtc.h> @@ -157,6 +159,32 @@ static void mainboard_enable(struct device *dev) hwm_setup(); } +static void mainboard_init(void *chip_info) +{ + int i; + struct device *dev; + + for (i = 1; i <= 3; i++) { + int ethernet_disable = 0; + char cmos_option_name[] = "ethernetx"; + snprintf(cmos_option_name, sizeof(cmos_option_name), + "ethernet%01d", i); + get_option(ðernet_disable, cmos_option_name); + if (!ethernet_disable) + continue; + printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n", i); + dev = dev_find_slot(0, PCI_DEVFN(28, i - 1)); + if (dev == NULL) { + printk(BIOS_ERR, + "Disabling Ethernet NIC: Cannot find 00:1c.%d!\n", + i - 1); + continue; + } + dev->enabled = 0; + } +} + struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index f0d4903bba..fda8f97848 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -165,8 +165,6 @@ static void early_superio_config_w83627thg(void) static void rcba_config(void) { - u32 reg32 = 0; - /* Set up virtual channel 0 */ /* Device 1f interrupt pin register */ @@ -184,50 +182,6 @@ static void rcba_config(void) /* Enable IOAPIC */ RCBA8(OIC) = 0x03; - /* Now, this is a bit ugly. As per PCI specification, function 0 of a - * device always has to be implemented. So disabling ethernet port 1 - * would essentially disable all three ethernet ports of the mainboard. - * It's possible to rename the ports to achieve compatibility to the - * PCI spec but this will confuse all (static!) tables containing - * interrupt routing information. - * To avoid this, we enable (unused) port 6 and swap it with port 1 - * in the case that ethernet port 1 is disabled. Since no devices - * are connected to that port, we don't have to worry about interrupt - * routing. - */ - int port_shuffle = 0; - - /* Disable unused devices */ - if (read_option(ethernet1, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n"); - reg32 |= FD_PCIE1; - } - if (read_option(ethernet2, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n"); - reg32 |= FD_PCIE2; - } else { - if (reg32 & FD_PCIE1) - port_shuffle = 1; - } - if (read_option(ethernet3, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n"); - reg32 |= FD_PCIE3; - } else { - if (reg32 & FD_PCIE1) - port_shuffle = 1; - } - - if (port_shuffle) { - /* Enable PCIE6 again */ - reg32 &= ~FD_PCIE6; - /* Swap PCIE6 and PCIE1 */ - RCBA32(RPFN) = 0x00043215; - } - - reg32 |= 1; - - RCBA32(FD) = reg32; - /* Enable PCIe Root Port Clock Gate */ } @@ -271,7 +225,6 @@ static void early_ich7_init(void) reg32 &= ~(3 << 0); reg32 |= (1 << 0); RCBA32(0x3430) = reg32; - RCBA32(FD) |= (1 << 0); RCBA16(0x0200) = 0x2008; RCBA8(0x2027) = 0x0d; RCBA16(0x3e08) |= (1 << 7); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index e664eb43fa..66d47ae157 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -272,12 +272,6 @@ int southbridge_detect_s3_resume(void); * Not all features might be disabled on * all chipsets. Esp. ICH-7U is picky. */ -#define FD_PCIE6 (1 << 21) -#define FD_PCIE5 (1 << 20) -#define FD_PCIE4 (1 << 19) -#define FD_PCIE3 (1 << 18) -#define FD_PCIE2 (1 << 17) -#define FD_PCIE1 (1 << 16) #define ICH_DISABLE_PCIE(x) (1 << (16 + (x))) #define FD_EHCI (1 << 15) #define FD_LPCB (1 << 14) |