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-rw-r--r--src/Kconfig10
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c1
-rw-r--r--src/mainboard/amd/serengeti_cheetah/ap_romstage.c1
-rw-r--r--src/mainboard/amd/serengeti_cheetah/romstage.c1
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c1
-rw-r--r--src/mainboard/amd/tilapia_fam10/romstage.c1
-rw-r--r--src/mainboard/asus/a8v-e_se/romstage.c2
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c2
-rw-r--r--src/mainboard/asus/m4a785-m/romstage.c1
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c1
-rw-r--r--src/mainboard/gigabyte/m57sli/ap_romstage.c1
-rw-r--r--src/mainboard/gigabyte/ma785gmt/romstage.c1
-rw-r--r--src/mainboard/gigabyte/ma78gm/romstage.c1
-rw-r--r--src/mainboard/iei/kino-780am2-fam10/romstage.c1
-rw-r--r--src/mainboard/iwill/dk8_htx/romstage.c1
-rw-r--r--src/mainboard/iwill/dk8s2/romstage.c1
-rw-r--r--src/mainboard/iwill/dk8x/romstage.c1
-rw-r--r--src/mainboard/jetway/pa78vm5/romstage.c1
-rw-r--r--src/mainboard/msi/ms7260/ap_romstage.c1
-rw-r--r--src/mainboard/msi/ms7260/romstage.c1
-rw-r--r--src/mainboard/msi/ms9185/romstage.c1
-rw-r--r--src/mainboard/msi/ms9282/romstage.c1
-rw-r--r--src/mainboard/nvidia/l1_2pvv/ap_romstage.c1
-rw-r--r--src/mainboard/supermicro/h8dme/ap_romstage.c1
-rw-r--r--src/mainboard/supermicro/h8dmr/ap_romstage.c1
-rw-r--r--src/mainboard/tyan/s2912/ap_romstage.c1
-rw-r--r--src/mainboard/via/epia-m700/romstage.c1
-rw-r--r--src/northbridge/amd/amdfam10/Kconfig1
-rw-r--r--src/northbridge/amd/amdfam10/debug.c2
-rw-r--r--src/northbridge/amd/amdk8/Kconfig1
-rw-r--r--src/northbridge/amd/amdk8/debug.c6
-rw-r--r--src/northbridge/via/vx800/examples/romstage.c1
32 files changed, 14 insertions, 35 deletions
diff --git a/src/Kconfig b/src/Kconfig
index be55b4bf90..00c5591d00 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -499,6 +499,16 @@ config DEBUG_RAM_SETUP
If unsure, say N.
+config HAVE_DEBUG_CAR
+ def_bool n
+
+config DEBUG_CAR
+ bool "Output verbose Cache-as-RAM debug messages"
+ default n
+ depends on HAVE_DEBUG_CAR
+ help
+ This option enables additional CAR related debug messages.
+
config DEBUG_PIRQ
bool "Check PIRQ table consistency"
default n
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index d7f8cb9c48..6f47f66283 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
index 5a9d7049dd..d8539932b2 100644
--- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
@@ -2,7 +2,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 65cabe9a4f..fed8d6a6c3 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 742700575b..b0a0f08829 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 2971a7fc8a..3e190fec9c 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 1f56947eed..aba667986f 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -24,8 +24,6 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
unsigned int get_sbdn(unsigned bus);
/* Used by raminit. */
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index cbf8ef570b..76b3e9db93 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -24,8 +24,6 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
unsigned int get_sbdn(unsigned bus);
/* Used by raminit. */
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index a0725eeb5b..770cee1cbe 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
index 7644ab49ba..1ecbd61be4 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
@@ -25,7 +25,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c
index d429b4cd31..0883a5a60f 100644
--- a/src/mainboard/gigabyte/m57sli/ap_romstage.c
+++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 9e221fc948..13664418ab 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 56133accd1..64b560d683 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 38d94a60d4..e53ddf4251 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 1af5c2c55f..8fea9d9abf 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 706014b9c2..77691a6ce2 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 706014b9c2..77691a6ce2 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 24302fe19a..b966c465e8 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -23,7 +23,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c
index 5b88a6d989..16b47685a6 100644
--- a/src/mainboard/msi/ms7260/ap_romstage.c
+++ b/src/mainboard/msi/ms7260/ap_romstage.c
@@ -24,7 +24,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1 /* Used by RAM init. */
#define QRANK_DIMM_SUPPORT 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 908138a5d3..2605a16c3f 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -20,7 +20,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
// #define RAM_TIMING_DEBUG 1
// #define DQS_TRAIN_DEBUG 1
// #define RES_DEBUG 1
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index a2bf78bf1b..522e2f3e11 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -24,7 +24,6 @@
*/
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index ed8ee85647..950f7dca59 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -23,7 +23,6 @@
*/
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
index 8d3cb8d9c7..5d6f45e328 100644
--- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c
index 8643bed96f..8e8b73bd2a 100644
--- a/src/mainboard/supermicro/h8dme/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dme/ap_romstage.c
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c
index 8643bed96f..8e8b73bd2a 100644
--- a/src/mainboard/supermicro/h8dmr/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c
index 99036d0716..e60992f88a 100644
--- a/src/mainboard/tyan/s2912/ap_romstage.c
+++ b/src/mainboard/tyan/s2912/ap_romstage.c
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index abf87a77fc..479305fa2e 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -23,7 +23,6 @@
*/
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define PAYLOAD_IS_SEABIOS 0
#include <stdint.h>
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 38eda7c37f..7e5b9dca4f 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -21,6 +21,7 @@ config NORTHBRIDGE_AMD_AMDFAM10
bool
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
+ select HAVE_DEBUG_CAR
select HYPERTRANSPORT_PLUGIN_SUPPORT
select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
select MMCONF_SUPPORT
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 7aa7751820..df4c079bbe 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -26,7 +26,7 @@
static inline void print_debug_addr(const char *str, void *val)
{
-#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if CONFIG_DEBUG_CAR
printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
#endif
}
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 02a23ab36e..77a08f2f46 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -21,6 +21,7 @@ config NORTHBRIDGE_AMD_AMDK8
bool
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
+ select HAVE_DEBUG_CAR
select HYPERTRANSPORT_PLUGIN_SUPPORT
config AGP_APERTURE_SIZE
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index 5cb996aa89..ee8050ea59 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -3,13 +3,9 @@
*
*/
-#ifndef CACHE_AS_RAM_ADDRESS_DEBUG
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-#endif
-
static inline void print_debug_addr(const char *str, void *val)
{
-#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if CONFIG_DEBUG_CAR
printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
#endif
}
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 63755c3181..48f7173e8d 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -21,7 +21,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#include <stdint.h>
#include <device/pci_def.h>