diff options
| -rw-r--r-- | src/mainboard/amd/olivehill/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/amd/olivehill/romstage.c | 78 |
2 files changed, 8 insertions, 71 deletions
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 3433115ad2..37fb43fdad 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -17,7 +17,6 @@ if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index d0e1938456..8190cb7711 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -17,31 +17,19 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { + int i; u32 val; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -50,67 +38,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); + /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for(i = 0; i < 200000; i++) + for (i = 0; i < 200000; i++) val = inb(0xcd6); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ } |