summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/mainboard/google/nyan/Kconfig3
-rw-r--r--src/mainboard/google/nyan_big/Kconfig3
-rw-r--r--src/mainboard/google/nyan_blaze/Kconfig3
-rw-r--r--src/soc/nvidia/tegra124/bootblock.c3
-rw-r--r--src/soc/nvidia/tegra124/include/soc/memlayout.ld3
-rw-r--r--src/soc/nvidia/tegra124/spi.c92
6 files changed, 14 insertions, 93 deletions
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index 8f0c9de4fc..a5ecf84cbc 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_NVIDIA_TEGRA124
select MAINBOARD_HAS_CHROMEOS
+ select COMMON_CBFS_SPI_WRAPPER
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select TEGRA124_MODEL_CD570M
@@ -26,6 +27,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
+ select SPI_FLASH_GIGADEVICE
+ select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS
diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
index b6f84f6b46..fdd40f6661 100644
--- a/src/mainboard/google/nyan_big/Kconfig
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_NVIDIA_TEGRA124
select MAINBOARD_HAS_CHROMEOS
select BOARD_ID_AUTO
+ select COMMON_CBFS_SPI_WRAPPER
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select TEGRA124_MODEL_CD570M
@@ -27,6 +28,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
+ select SPI_FLASH_GIGADEVICE
+ select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS
diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig
index 0fd763deb8..f28fb24413 100644
--- a/src/mainboard/google/nyan_blaze/Kconfig
+++ b/src/mainboard/google/nyan_blaze/Kconfig
@@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_ARM
select BOARD_ID_AUTO
+ select COMMON_CBFS_SPI_WRAPPER
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select SOC_NVIDIA_TEGRA124
@@ -28,6 +29,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
+ select SPI_FLASH_GIGADEVICE
+ select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index cebe405522..2a526a7748 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -24,6 +24,7 @@
#include <soc/nvidia/tegra/apbmisc.h>
#include <soc/pinmux.h>
#include <soc/power.h>
+#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void run_next_stage(void *entry)
@@ -81,6 +82,8 @@ void main(void)
PINMUX_PWR_INT_N_FUNC_PMICINTR |
PINMUX_INPUT_ENABLE);
+ timestamp_init(0);
+
run_romstage();
}
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index c3f5f4ec42..5bab362396 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -33,7 +33,8 @@ SECTIONS
STACK(0x4000E000, 8K)
BOOTBLOCK(0x40010000, 24K)
VERSTAGE(0x40016000, 72K)
- ROMSTAGE(0x40028000, 96K)
+ ROMSTAGE(0x40028000, 95K)
+ TIMESTAMP(0x4003FC00, 1K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index d5f786141e..d5be4a6034 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -798,69 +798,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return ret;
}
-#define JEDEC_READ 0x03
-#define JEDEC_READ_OUTSIZE 0x04
-#define JEDEC_FAST_READ_DUAL 0x3b
-#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05
-
-static struct spi_slave *boot_slave;
-
-static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
-{
- u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE];
- unsigned int read_cmd_bytes;
- int ret = count;
- struct tegra_spi_channel *channel;
-
- channel = to_tegra_spi(boot_slave->bus);
-
- if (channel->dual_mode) {
- /*
- * Command 0x3b will interleave data only, command 0xbb will
- * interleave the address as well. It's nice to see the address
- * plainly when debugging, and we're mostly concerned with
- * large transfers so the optimization of using 0xbb isn't
- * really worthwhile.
- */
- spi_read_cmd[0] = JEDEC_FAST_READ_DUAL;
- spi_read_cmd[4] = 0x00; /* dummy byte */
- read_cmd_bytes = JEDEC_FAST_READ_DUAL_OUTSIZE;
- } else {
- spi_read_cmd[0] = JEDEC_READ;
- read_cmd_bytes = JEDEC_READ_OUTSIZE;
- }
- spi_read_cmd[1] = (offset >> 16) & 0xff;
- spi_read_cmd[2] = (offset >> 8) & 0xff;
- spi_read_cmd[3] = offset & 0xff;
-
- spi_claim_bus(boot_slave);
-
- if (spi_xfer(boot_slave, spi_read_cmd,
- read_cmd_bytes, NULL, 0) < 0) {
- ret = -1;
- printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
- __func__, sizeof(spi_read_cmd));
- goto tegra_spi_cbfs_read_exit;
- }
-
- if (channel->dual_mode) {
- setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
- }
- if (spi_xfer(boot_slave, NULL, 0, dest, count)) {
- ret = -1;
- printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
- __func__, count);
- }
- if (channel->dual_mode)
- clrbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
-
-tegra_spi_cbfs_read_exit:
- /* de-assert /CS */
- spi_release_bus(boot_slave);
- return ret;
-}
-
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
{
struct tegra_spi_channel *channel = to_tegra_spi(bus);
@@ -869,32 +806,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &channel->slave;
}
-
-static const struct region_device_ops tegra_spi_ops = {
- .mmap = mmap_helper_rdev_mmap,
- .munmap = mmap_helper_rdev_munmap,
- .readat = tegra_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &mdev.rdev;
-}
-
-void boot_device_init(void)
-{
- struct tegra_spi_channel *boot_chan;
-
- boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
- boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
-
-#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
- boot_chan->dual_mode = 1;
-#endif
- boot_slave = &boot_chan->slave;
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 20:14:35 +0000