diff options
41 files changed, 54 insertions, 54 deletions
diff --git a/src/soc/broadcom/cygnus/bootblock.c b/src/soc/broadcom/cygnus/bootblock.c index 6a8a7d2c16..d24895e49d 100644 --- a/src/soc/broadcom/cygnus/bootblock.c +++ b/src/soc/broadcom/cygnus/bootblock.c @@ -22,8 +22,8 @@ void bootblock_soc_init(void) { /* - * not only for speed but for preventing the cpu from crashing. - * the cpu is not happy when cache is cleaned without mmu turned on. + * not only for speed but for preventing the CPU from crashing. + * the CPU is not happy when cache is cleaned without mmu turned on. */ mmu_init(); mmu_config_range(0, 4096, DCACHE_OFF); diff --git a/src/soc/dmp/vortex86ex/northbridge.c b/src/soc/dmp/vortex86ex/northbridge.c index 62c68e062e..e60481c785 100644 --- a/src/soc/dmp/vortex86ex/northbridge.c +++ b/src/soc/dmp/vortex86ex/northbridge.c @@ -89,7 +89,7 @@ static void pci_domain_set_resources(device_t dev) ss = pci_read_config16(mc_dev, 0x6c); ss = ((ss >> 8) & 0xf); tomk = (2 * 1024) << ss; - printk(BIOS_DEBUG, "I would set ram size to %ld Mbytes\n", (tomk >> 10)); + printk(BIOS_DEBUG, "I would set RAM size to %ld Mbytes\n", (tomk >> 10)); /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index f2a7e76f20..030d3ebaec 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -146,8 +146,8 @@ scope (\_SB) { Scope(\_GPE) { /* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads - * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in acpi enable - * register at 0x430. For APL acpi enable register DW0 i.e., ACPI + * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable + * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI * GPE0a_EN at 0x430 is reserved. */ Method(_L0F, 0) {} diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 3ad2110ded..436cc33477 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -185,11 +185,11 @@ void iosf_ssus_write(int reg, uint32_t val); #define BNOCACHE 0x23 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ #define BUNIT_BMBOUND 0x25 -/* BMBOUND_HI describes the available ram above 4GiB. It has a +/* BMBOUND_HI describes the available RAM above 4GiB. It has a * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB * granularity care needs to be taken with the e820 map to account for a hole - * in the ram. */ + * in the RAM. */ #define BUNIT_BMBOUND_HI 0x26 #define BUNIT_MMCONF_REG 0x27 /* The SMMRR registers define the SMM region in MiB granularity. */ diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 96ae86dd63..2b5174435b 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -305,7 +305,7 @@ static void *setup_stack_and_mttrs(void) num_mtrrs++; top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the + /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the * start of the TSEG region. It is required to be 8MiB aligned. Set * this area as cacheable so it can be used later for ramstage before * setting up the entire RAM as cacheable. */ @@ -315,7 +315,7 @@ static void *setup_stack_and_mttrs(void) slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; - /* Cache 8MiB at the top of ram. Top of ram is where the TSEG + /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG * region resides. However, it is not restricted to SMM mode until * SMM has been relocated. By setting the region to cacheable it * provides faster access when relocating the SMM handler as well diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7fa4b790fd..4dca11019e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -100,7 +100,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE default 0x800 help The amount of anticipated stack usage from the data cache - during pre-ram rom stage execution. + during pre-ram ROM stage execution. config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index 5afca3e123..c0b3f06cc2 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -122,11 +122,11 @@ void reg_script_write_iosf(struct reg_script_context *ctx); /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ #define BUNIT_BMBOUND 0x25 /* - * BMBOUND_HI describes the available ram above 4GiB. It has a + * BMBOUND_HI describes the available RAM above 4GiB. It has a * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB * granularity care needs to be taken with the e820 map to account for a hole - * in the ram. + * in the RAM. */ #define BUNIT_BMBOUND_HI 0x26 #define BUNIT_MMCONF_REG 0x27 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 545eb62058..2d6176af6b 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -109,7 +109,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE default 0x2000 help The amount of anticipated stack usage from the data cache - during pre-ram rom stage execution. + during pre-ram ROM stage execution. config HAVE_MRC bool "Add a Memory Reference Code binary" diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 2afdfadc3e..16f350c993 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -576,7 +576,7 @@ static void cpu_core_init(device_t cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 37d7f30a68..24720d14a3 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -147,7 +147,7 @@ clear_mtrrs: wrmsr post_code(0x27) - /* Enable caching for ram init code to run faster */ + /* Enable caching for RAM init code to run faster */ movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index 76307cfbb5..86a1c02b15 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -78,7 +78,7 @@ void *setup_stack_and_mttrs(void) num_mtrrs++; top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the + /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the * start of the TSEG region. It is required to be 8MiB aligned. Set * this area as cacheable so it can be used later for ramstage before * setting up the entire RAM as cacheable. */ @@ -88,7 +88,7 @@ void *setup_stack_and_mttrs(void) slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; - /* Cache 8MiB at the top of ram. Top of ram is where the TSEG + /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG * region resides. However, it is not restricted to SMM mode until * SMM has been relocated. By setting the region to cacheable it * provides faster access when relocating the SMM handler as well diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 6fd609b508..873e909c85 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -136,7 +136,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* Determine if the processor supports saving state in MSRs. If so, * enable it before the non-BSPs run so that SMM relocation can occur diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index 03c63575d0..dc59ab7756 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -21,7 +21,7 @@ void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region. - * The top of ram is defined to be the TSEG base address. */ + * The top of RAM is defined to be the TSEG base address. */ u32 offset = smm_region_size(); offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index 63566db6c8..845e0f0ae4 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -85,7 +85,7 @@ acpi_cstate_t *soc_get_cstate_map(int *num_entries); acpi_tstate_t *soc_get_tss_table(int *num_entries); /* - * soc_get_acpi_base_address returns the acpi base address for the SOC + * soc_get_acpi_base_address returns the ACPI base address for the SOC */ uint16_t soc_get_acpi_base_address(void); diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h index 6b64690674..c019286065 100644 --- a/src/soc/intel/common/gma.h +++ b/src/soc/intel/common/gma.h @@ -53,7 +53,7 @@ typedef struct { #define SBIOS_VERSION_SIZE 32 -/* mailbox 1: public acpi methods */ +/* mailbox 1: public ACPI methods */ typedef struct { u32 drdy; u32 csts; diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 3fba0b7808..742b2ef794 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -94,7 +94,7 @@ static void pre_mp_init(void) { x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/soc/intel/fsp_baytrail/include/soc/iosf.h b/src/soc/intel/fsp_baytrail/include/soc/iosf.h index a220469cd2..0982da68db 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/iosf.h +++ b/src/soc/intel/fsp_baytrail/include/soc/iosf.h @@ -186,11 +186,11 @@ void iosf_ssus_write(int reg, uint32_t val); #define BNOCACHE 0x23 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ #define BUNIT_BMBOUND 0x25 -/* BMBOUND_HI describes the available ram above 4GiB. It has a +/* BMBOUND_HI describes the available RAM above 4GiB. It has a * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB * granularity care needs to be taken with the e820 map to account for a hole - * in the ram. */ + * in the RAM. */ #define BUNIT_BMBOUND_HI 0x26 #define BUNIT_MMCONF_REG 0x27 /* The SMMRR registers define the SMM region in MiB granularity. */ diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 881ad0b9b5..a7ed414da8 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -244,7 +244,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) late_mainboard_romstage_entry(); post_code(0x4c); - /* if S3 resume skip ram check */ + /* if S3 resume skip RAM check */ if (prev_sleep_state != ACPI_S3) { quick_ram_check(); post_code(0x4d); diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index ca082041e9..1e4ec34858 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -31,7 +31,7 @@ static void pre_mp_init(void) { x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c index a770c81bf1..eb8c46ecf2 100644 --- a/src/soc/intel/quark/tsc_freq.c +++ b/src/soc/intel/quark/tsc_freq.c @@ -20,7 +20,7 @@ static unsigned long bus_freq_khz(void) { - /* cpu freq = 400 MHz */ + /* CPU freq = 400 MHz */ return 400 * 1000; } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index b7353cab6b..2b75e5aeb4 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -352,7 +352,7 @@ static void cpu_core_init(device_t cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); @@ -487,7 +487,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * 0x08b with the Patch revision id one less than the id in the * microcode binary. The PRMRR support is indicated in the MSR * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during cpu initialization. + * same microcode during CPU initialization. */ msr = rdmsr(MTRR_CAP_MSR); return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 807aaa38ac..1cc8e54e55 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -138,7 +138,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* * Determine if the processor supports saving state in MSRs. If so, diff --git a/src/soc/marvell/armada38x/bootblock_asm.S b/src/soc/marvell/armada38x/bootblock_asm.S index 640c4ed91e..7bb7ccf504 100644 --- a/src/soc/marvell/armada38x/bootblock_asm.S +++ b/src/soc/marvell/armada38x/bootblock_asm.S @@ -29,7 +29,7 @@ maskrom_param: ENTRY(_start) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/marvell/bg4cd/romstage.S b/src/soc/marvell/bg4cd/romstage.S index 9a7a68e283..73574f2bc4 100644 --- a/src/soc/marvell/bg4cd/romstage.S +++ b/src/soc/marvell/bg4cd/romstage.S @@ -33,7 +33,7 @@ .arm ENTRY(stage_entry) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 2a526a7748..ce41242299 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -34,7 +34,7 @@ static void run_next_stage(void *entry) power_enable_and_ungate_cpu(); - /* Repair ram on cluster0 and cluster1 after CPU is powered on. */ + /* Repair RAM on cluster0 and cluster1 after CPU is powered on. */ ram_repair(); clock_cpu0_remove_reset(); diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S index 5484450f02..0391ebf1ac 100644 --- a/src/soc/nvidia/tegra124/bootblock_asm.S +++ b/src/soc/nvidia/tegra124/bootblock_asm.S @@ -28,7 +28,7 @@ ENTRY(_start) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h index 2d0ba7d7c1..a67a009945 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h @@ -791,9 +791,9 @@ struct sdram_params { uint32_t EmcCaTrainingTimingCntl2; /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot rom write */ + /* Specifies enable and offset for patched boot ROM write */ uint32_t BootRomPatchControl; - /* Specifies data for patched boot rom write */ + /* Specifies data for patched boot ROM write */ uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ uint32_t McMtsCarveoutBom; diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 8a0d038712..2737b282e0 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -612,7 +612,7 @@ void lp0_resume(void) power_on_main_cpu(); - // Perform ram repair after cpu is powered on. + // Perform RAM repair after CPU is powered on. ram_repair(); clear_cpu_resets(); diff --git a/src/soc/nvidia/tegra124/maincpu.S b/src/soc/nvidia/tegra124/maincpu.S index 11367480ad..fc32ed2637 100644 --- a/src/soc/nvidia/tegra124/maincpu.S +++ b/src/soc/nvidia/tegra124/maincpu.S @@ -32,7 +32,7 @@ .arm ENTRY(maincpu_setup) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra132/bootblock_asm.S b/src/soc/nvidia/tegra132/bootblock_asm.S index 857900a6eb..62554422db 100644 --- a/src/soc/nvidia/tegra132/bootblock_asm.S +++ b/src/soc/nvidia/tegra132/bootblock_asm.S @@ -30,7 +30,7 @@ ENTRY(_start) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index 5a307b57bb..95f91d8f8d 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -133,14 +133,14 @@ static void request_ram_repair(void) stopwatch_init(&sw); - /* Perform cluster 0 ram repair */ + /* Perform cluster 0 RAM repair */ reg = read32(&flow->ram_repair); reg |= req; write32(&flow->ram_repair, reg); while ((read32(&flow->ram_repair) & sts) != sts) ; - /* Perform cluster 1 ram repair */ + /* Perform cluster 1 RAM repair */ reg = read32(&flow->ram_repair_cluster1); reg |= req; write32(&flow->ram_repair_cluster1, reg); diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 0db120d8d2..be12b856b1 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -508,7 +508,7 @@ void clock_cpu0_config(void) /* wait and try again */ if (timeout >= CLK_SWITCH_TIMEOUT_US) { printk(BIOS_ERR, "%s: PLLX programming timeout. " - "Switching cpu clock has falied.\n", + "Switching CPU clock has falied.\n", __func__); break; } diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_param.h b/src/soc/nvidia/tegra132/include/soc/sdram_param.h index 6bc5aeaf49..ce85058383 100644 --- a/src/soc/nvidia/tegra132/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra132/include/soc/sdram_param.h @@ -794,9 +794,9 @@ struct sdram_params { /* Set if bit 6 select is greater than bit 7 select; uses aremc. spec packet SWIZZLE_BIT6_GT_BIT7 */ uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot rom write */ + /* Specifies enable and offset for patched boot ROM write */ uint32_t BootRomPatchControl; - /* Specifies data for patched boot rom write */ + /* Specifies data for patched boot ROM write */ uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ uint32_t McMtsCarveoutBom; diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c index 94d22634a4..bd4e5c4218 100644 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c @@ -645,7 +645,7 @@ void lp0_resume(void) power_on_main_cpu(); - // Perform ram repair after cpu is powered on. + // Perform RAM repair after CPU is powered on. ram_repair(); clear_cpu_resets(); diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 3b45aff63d..c5c1392c07 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -72,7 +72,7 @@ void romstage(void) cbmem_initialize_empty(); ccplex_cpu_prepare(); - printk(BIOS_INFO, "T132 romstage: cpu prepare done\n"); + printk(BIOS_INFO, "T132 romstage: CPU prepare done\n"); ccplex_load_mts(); printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); diff --git a/src/soc/nvidia/tegra210/bootblock_asm.S b/src/soc/nvidia/tegra210/bootblock_asm.S index 857900a6eb..62554422db 100644 --- a/src/soc/nvidia/tegra210/bootblock_asm.S +++ b/src/soc/nvidia/tegra210/bootblock_asm.S @@ -30,7 +30,7 @@ ENTRY(_start) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index a652b7624e..8759c73227 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -72,7 +72,7 @@ static void request_ram_repair(void) stopwatch_init(&sw); - /* Perform ram repair */ + /* Perform RAM repair */ reg = read32(&flow->ram_repair); reg |= req; write32(&flow->ram_repair, reg); diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 667d090118..dee7c7caab 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -951,9 +951,9 @@ struct sdram_params { /* Set if bit 6 select is greater than bit 7 select; uses aremc. spec packet SWIZZLE_BIT6_GT_BIT7 */ uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot rom write */ + /* Specifies enable and offset for patched boot ROM write */ uint32_t BootRomPatchControl; - /* Specifies data for patched boot rom write */ + /* Specifies data for patched boot ROM write */ uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 15477d6fe2..d3ac67b00f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -1024,7 +1024,7 @@ void lp0_resume(void) * 1 : MAX77621 */ if (read32(pmc_scratch201_ptr) & PMIC_77621) - /* Set cpu rail 0.85V */ + /* Set CPU rail 0.85V */ i2c_send(MAX77621_I2C_ADDR, MAX77621_VOUT_DATA); else /* Enable GPIO5 on MAX77620 PMIC */ diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index c9ff35bfb5..9491570a0b 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -79,7 +79,7 @@ void romstage(void) cbmem_initialize_empty(); ccplex_cpu_prepare(); - printk(BIOS_INFO, "T210 romstage: cpu prepare done\n"); + printk(BIOS_INFO, "T210 romstage: CPU prepare done\n"); romstage_mainboard_init(); diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 5d701bb2cf..7731857e73 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -200,7 +200,7 @@ static void low_power_start(void) if (reg_val != RST_FLAG_VAL) { write32(VECTOR_LOW_POWER_FLAG, 0x0); jump_bx(CORE_RESET_INIT_ADDRESS); - /* restart cpu execution and never returns. */ + /* restart CPU execution and never returns. */ } /* Workaround for iROM EVT1. A7 core execution may flow into incorrect @@ -276,7 +276,7 @@ static void configure_secondary_cores(void) * WFI state (in bootblock). The power_down_core will be more helpful * when we want to use SMP inside firmware. */ - /* Clear boot reg (hotplug address) in cpu states */ + /* Clear boot reg (hotplug address) in CPU states */ write32((void *)&exynos_cpu_states->hotplug_address, 0); /* set low_power flag and address */ |