diff options
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 12 |
4 files changed, 48 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index e14f843f9f..405eb5d324 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -72,7 +73,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; - u32 tomk, tolud, uma_sizek = 0; + u32 tomk, tolud, uma_sizek = 0, delta_cbmem; u32 pcie_config_base, pcie_config_size; /* Total Memory 2GB example: @@ -138,6 +139,15 @@ static void mch_domain_read_resources(struct device *dev) tomk -= tseg_sizek; uma_sizek += tseg_sizek; + /* cbmem_top can be shifted downwards due to alignment. + Mark the region between cbmem_top and tomk as unusable */ + delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + tomk -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); /* Report the memory regions */ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 110a9efc53..de55cc35f2 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -59,7 +60,7 @@ static int get_pcie_bar(u32 *base) static void mch_domain_read_resources(struct device *dev) { - uint32_t pci_tolm, tseg_sizek; + uint32_t pci_tolm, tseg_sizek, cbmem_topk, delta_cbmem; uint8_t tolud; uint16_t reg16; unsigned long long tomk, tomk_stolen; @@ -104,6 +105,16 @@ static void mch_domain_read_resources(struct device *dev) tseg_memory_base = tomk_stolen * 1024ULL; tseg_memory_size = tseg_sizek * 1024ULL; + /* cbmem_top can be shifted downwards due to alignment. + Mark the region between cbmem_top and tomk as unusable */ + cbmem_topk = ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk_stolen - cbmem_topk; + tomk_stolen -= delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + + /* The following needs to be 2 lines, otherwise the second * number is always 0 */ @@ -115,6 +126,7 @@ static void mch_domain_read_resources(struct device *dev) ram_resource(dev, 4, 768, (tomk - 768)); uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); + uma_resource(dev, 7, cbmem_topk, delta_cbmem); } static void mch_domain_set_resources(struct device *dev) diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 4775b155e2..2647bcc968 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -55,7 +56,7 @@ static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; u32 tomk, tolud, tseg_sizek; - u32 pcie_config_base, pcie_config_size; + u32 pcie_config_base, pcie_config_size, cbmem_topk, delta_cbmem; u16 index; const u32 top32memk = 4 * (GiB / KiB); @@ -100,6 +101,16 @@ static void mch_domain_read_resources(struct device *dev) /* Subtract TSEG size */ tseg_sizek = gtt_basek - tseg_basek; tomk -= tseg_sizek; + printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); + + /* cbmem_top can be shifted downwards due to alignment. + Mark the region between cbmem_top and tomk as unusable */ + cbmem_topk = (uint32_t)cbmem_top() >> 10; + delta_cbmem = tomk - cbmem_topk; + tomk -= delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", + delta_cbmem); /* Report the memory regions */ ram_resource(dev, index++, 0, 640); @@ -107,6 +118,7 @@ static void mch_domain_read_resources(struct device *dev) reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); reserved_ram_resource(dev, index++, igd_basek, gms_sizek); + reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); /* * If > 4GB installed then memory from TOLUD to 4GB diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index d1926b29f9..bc7a5b39ae 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -35,7 +36,7 @@ static void mch_domain_read_resources(struct device *dev) { u8 index, reg8; u64 tom, touud; - u32 tomk, tseg_sizek = 0, tolud; + u32 tomk, tseg_sizek = 0, tolud, delta_cbmem; u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0; @@ -100,6 +101,15 @@ static void mch_domain_read_resources(struct device *dev) printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10); + /* cbmem_top can be shifted downwards due to alignment. + Mark the region between cbmem_top and tomk as unusable */ + delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + tomk -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); /* Report the memory regions */ |