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-rw-r--r--src/mainboard/lenovo/x60/i915.c106
-rw-r--r--src/mainboard/lenovo/x60/i915_reg.h186
-rw-r--r--src/mainboard/lenovo/x60/i915io.c164
-rw-r--r--src/mainboard/lenovo/x60/i915io.h3
-rw-r--r--src/mainboard/lenovo/x60/intel_dp.c12
-rw-r--r--src/mainboard/lenovo/x60/mainboard.c2
-rw-r--r--src/northbridge/intel/i945/gma.c2
7 files changed, 240 insertions, 235 deletions
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index 837c8b490c..0f90168b17 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -57,14 +57,10 @@ static unsigned int graphics;
static unsigned short addrport;
static unsigned short dataport;
static unsigned int physbase;
-#if 0 //undefined reference
-extern int oprom_is_loaded;
-#else
int oprom_is_loaded;
-#endif
-#define PGETBL_CTL 0x2020
-#define PGETBL_ENABLED 0x00000001
+#define PGETBL_CTL 0x2020
+#define PGETBL_ENABLED 0x00000001
static u32 htotal, hblank, hsync, vtotal, vblank, vsync;
@@ -126,36 +122,37 @@ setgtt(int start, int end, unsigned long base, int inc)
{
int i;
- printk(BIOS_INFO, "%s(%d,%d,0x%08lx,%d);\n",__func__, start, end, base, inc);
+ printk(BIOS_INFO, "%s(%d,%d,0x%08lx,%d);\n",
+ __func__, start, end, base, inc);
- for(i = start; i < end; i++){
+ for (i = start; i < end; i++) {
u32 word = base + i*inc;
- WRITE32(word|1,(i*4)|1);
+ WRITE32(word|1, (i*4)|1);
}
}
int gtt_setup(unsigned int mmiobase);
int gtt_setup(unsigned int mmiobase)
{
- unsigned long PGETBL_save;
+ unsigned long PGETBL_save;
- PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
- PGETBL_save |= PGETBL_ENABLED;
+ PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
+ PGETBL_save |= PGETBL_ENABLED;
- printk(BIOS_DEBUG, "PGETBL_save=0x%lx\n",PGETBL_save );
+ printk(BIOS_DEBUG, "PGETBL_save=0x%lx\n", PGETBL_save);
- write32(mmiobase + GFX_FLSH_CNTL, 0);
+ write32(mmiobase + GFX_FLSH_CNTL, 0);
- write32(mmiobase + PGETBL_CTL, PGETBL_save);
+ write32(mmiobase + PGETBL_CTL, PGETBL_save);
- /* verify */
- if ( read32( mmiobase + PGETBL_CTL) & PGETBL_ENABLED ){
- printk(BIOS_DEBUG, "gtt_setup is enabled!!!\n");
- }else{
+ /* verify */
+ if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {
+ printk(BIOS_DEBUG, "gtt_setup is enabled.\n");
+ } else {
printk(BIOS_DEBUG, "gtt_setup failed!!!\n");
return 1;
}
- write32(mmiobase + GFX_FLSH_CNTL, 0);
+ write32(mmiobase + GFX_FLSH_CNTL, 0);
return 0;
}
@@ -188,9 +185,8 @@ static void palette(void)
int i;
unsigned long color = 0;
- for(i = 0; i < 256; i++, color += 0x010101){
+ for (i = 0; i < 256; i++, color += 0x010101)
io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2));
- }
}
int vbe_mode_info_valid(void);
@@ -202,7 +198,8 @@ int vbe_mode_info_valid(void)
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{
- printk(BIOS_SPEW, "fill_lb_framebuffer: graphics is %p\n", (void *)graphics);
+ printk(BIOS_SPEW, "fill_lb_framebuffer: graphics is %p\n",
+ (void *)graphics);
framebuffer->physical_address = graphics;
framebuffer->x_resolution = 1024;
framebuffer->y_resolution = 768;
@@ -228,10 +225,11 @@ static int run(int index)
if (index >= niodefs)
return index;
/* state machine! */
- for(i = index, id = &iodefs[i]; id->op; i++, id++){
- switch(id->op){
+ for (i = index, id = &iodefs[i]; id->op; i++, id++) {
+ switch (id->op) {
case M:
- if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n",
+ if (verbose & vmsg)
+ printk(BIOS_SPEW, "%ld: %s\n",
globalmicroseconds(), id->msg);
break;
case P:
@@ -242,15 +240,16 @@ static int run(int index)
if (verbose & vio)
printk(BIOS_SPEW, "\texpect %08lx\n", id->data);
/* we're looking for something. */
- if (lastidread->addr == id->addr){
+ if (lastidread->addr == id->addr) {
/* they're going to be polling.
* just do it 1000 times
*/
- for (t = 0; t < 1000 && id->data != u; t++){
+ for (t = 0; t < 1000 && id->data != u; t++)
u = READ32(id->addr);
- }
- if (verbose & vspin) printk(BIOS_SPEW,
- "%s: # loops %ld got %08lx want %08lx\n",
+
+ if (verbose & vspin)
+ printk(BIOS_SPEW,
+ "%s: # loops %ld got %08lx want %08lx\n",
regname(id->addr),
t, u, id->data);
}
@@ -258,20 +257,24 @@ static int run(int index)
break;
case W:
WRITE32(id->data, id->addr);
- if (id->addr == PCH_PP_CONTROL){
+ if (id->addr == PCH_PP_CONTROL) {
if (verbose & vio)
printk(BIOS_SPEW, "PCH_PP_CONTROL\n");
- switch(id->data & 0xf){
- case 8: break;
- case 7: break;
- default: udelay(100000);
+ switch (id->data & 0xf) {
+ case 8:
+ break;
+ case 7:
+ break;
+ default:
+ udelay(100000);
if (verbose & vio)
- printk(BIOS_SPEW, "U %d\n", 100000);
+ printk(BIOS_SPEW, "U %d\n",
+ 100000);
}
}
break;
case V:
- if (id->count < 8){
+ if (id->count < 8) {
prev = verbose;
verbose = id->count;
} else {
@@ -284,7 +287,8 @@ static int run(int index)
return i+1;
break;
default:
- printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i);
+ printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n",
+ id->op, i);
return -1;
}
if (id->udelay)
@@ -311,31 +315,33 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
dataport = addrport + 4;
physbase = pphysbase;
graphics = pgfx;
- printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p"
- "addrport %04x physbase %08x\n",
+ printk(BIOS_SPEW,
+ "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
(void *)graphics, mmio, addrport, physbase);
globalstart = rdtscll();
- decode_edid((unsigned char *)&x60_edid_data, sizeof(x60_edid_data), &edid);
+ decode_edid((unsigned char *)&x60_edid_data,
+ sizeof(x60_edid_data), &edid);
- htotal = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
+ htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
- hblank = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
+ hblank = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank);
hsync = (edid.ha + edid.hso - 1) |
- ((edid.ha + edid.hso + edid.hspw- 1) << 16);
+ ((edid.ha + edid.hso + edid.hspw - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync);
- vtotal = (edid.va - 1) | ((edid.va + edid.vbl- 1) << 16);
+ vtotal = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal);
- vblank = (edid.va - 1) | ((edid.va + edid.vbl- 1) << 16);
+ vblank = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank);
- vsync = (edid.va + edid.vso - 1) |((edid.va + edid.vso + edid.vspw- 1) << 16);
+ vsync = (edid.va + edid.vso - 1) |
+ ((edid.va + edid.vso + edid.vspw - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync);
printk(BIOS_SPEW, "Table has %d elements\n", niodefs);
@@ -368,7 +374,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
* starting at physbase.
*/
- if ( gtt_setup(pmmio) ){
+ if (gtt_setup(pmmio)) {
printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
return 0;
}
@@ -376,7 +382,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
setgtt(0, 800 , physbase, 4096);
temp = READ32(PGETLB_CTL);
- printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp);
+ printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp);
if (temp & 1)
printk(BIOS_INFO, "GTT Enabled\n");
diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h
index a5c08d6e41..382b822c7b 100644
--- a/src/mainboard/lenovo/x60/i915_reg.h
+++ b/src/mainboard/lenovo/x60/i915_reg.h
@@ -39,65 +39,65 @@
/* PCI config space */
#define HPLLCC 0xc0 /* 855 only */
-#define GC_CLOCK_CONTROL_MASK (0xf << 0)
-#define GC_CLOCK_133_200 (0 << 0)
-#define GC_CLOCK_100_200 (1 << 0)
-#define GC_CLOCK_100_133 (2 << 0)
-#define GC_CLOCK_166_250 (3 << 0)
-#define GCFGC2 0xda
-#define GCFGC 0xf0 /* 915+ only */
-#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
-#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
-#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
-#define GC_DISPLAY_CLOCK_MASK (7 << 4)
-#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
-#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
-#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
-#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
-#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
-#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
-#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
-#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
-#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
-#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
-#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
-#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
-#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
-#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
-#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
-#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
-#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
-#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
-#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
-#define LBB 0xf4
+#define GC_CLOCK_CONTROL_MASK (0xf << 0)
+#define GC_CLOCK_133_200 (0 << 0)
+#define GC_CLOCK_100_200 (1 << 0)
+#define GC_CLOCK_100_133 (2 << 0)
+#define GC_CLOCK_166_250 (3 << 0)
+#define GCFGC2 0xda
+#define GCFGC 0xf0 /* 915+ only */
+#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
+#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
+#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
+#define GC_DISPLAY_CLOCK_MASK (7 << 4)
+#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
+#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
+#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
+#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
+#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
+#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
+#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
+#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
+#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
+#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
+#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
+#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
+#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
+#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
+#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
+#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
+#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
+#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
+#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
+#define LBB 0xf4
/* Graphics reset regs */
-#define I965_GDRST 0xc0 /* PCI config register */
-#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
-#define GRDOM_FULL (0<<2)
-#define GRDOM_RENDER (1<<2)
-#define GRDOM_MEDIA (3<<2)
+#define I965_GDRST 0xc0 /* PCI config register */
+#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
+#define GRDOM_FULL (0<<2)
+#define GRDOM_RENDER (1<<2)
+#define GRDOM_MEDIA (3<<2)
#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
-#define GEN6_MBC_SNPCR_SHIFT 21
-#define GEN6_MBC_SNPCR_MASK (3<<21)
-#define GEN6_MBC_SNPCR_MAX (0<<21)
-#define GEN6_MBC_SNPCR_MED (1<<21)
-#define GEN6_MBC_SNPCR_LOW (2<<21)
-#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
-
-#define GEN6_MBCTL 0x0907c
-#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
-#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
-#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
-#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
-#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
-
-#define GEN6_GDRST 0x941c
-#define GEN6_GRDOM_FULL (1 << 0)
-#define GEN6_GRDOM_RENDER (1 << 1)
-#define GEN6_GRDOM_MEDIA (1 << 2)
-#define GEN6_GRDOM_BLT (1 << 3)
+#define GEN6_MBC_SNPCR_SHIFT 21
+#define GEN6_MBC_SNPCR_MASK (3<<21)
+#define GEN6_MBC_SNPCR_MAX (0<<21)
+#define GEN6_MBC_SNPCR_MED (1<<21)
+#define GEN6_MBC_SNPCR_LOW (2<<21)
+#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
+
+#define GEN6_MBCTL 0x0907c
+#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
+#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
+#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
+#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
+#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
+
+#define GEN6_GDRST 0x941c
+#define GEN6_GRDOM_FULL (1 << 0)
+#define GEN6_GRDOM_RENDER (1 << 1)
+#define GEN6_GRDOM_MEDIA (1 << 2)
+#define GEN6_GRDOM_BLT (1 << 3)
/* PPGTT stuff */
#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
@@ -118,43 +118,43 @@
#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
-#define PP_DIR_DCLV_2G 0xffffffff
+#define PP_DIR_DCLV_2G 0xffffffff
#define GAM_ECOCHK 0x4090
-#define ECOCHK_SNB_BIT (1<<10)
-#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
-#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
+#define ECOCHK_SNB_BIT (1<<10)
+#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
+#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
/* VGA stuff */
-#define VGA_ST01_MDA 0x3ba
-#define VGA_ST01_CGA 0x3da
+#define VGA_ST01_MDA 0x3ba
+#define VGA_ST01_CGA 0x3da
-#define VGA_MSR_WRITE 0x3c2
-#define VGA_MSR_READ 0x3cc
-#define VGA_MSR_MEM_EN (1<<1)
-#define VGA_MSR_CGA_MODE (1<<0)
+#define VGA_MSR_WRITE 0x3c2
+#define VGA_MSR_READ 0x3cc
+#define VGA_MSR_MEM_EN (1<<1)
+#define VGA_MSR_CGA_MODE (1<<0)
-#define VGA_SR_INDEX 0x3c4
-#define VGA_SR_DATA 0x3c5
+#define VGA_SR_INDEX 0x3c4
+#define VGA_SR_DATA 0x3c5
-#define VGA_AR_INDEX 0x3c0
-#define VGA_AR_VID_EN (1<<5)
-#define VGA_AR_DATA_WRITE 0x3c0
-#define VGA_AR_DATA_READ 0x3c1
+#define VGA_AR_INDEX 0x3c0
+#define VGA_AR_VID_EN (1<<5)
+#define VGA_AR_DATA_WRITE 0x3c0
+#define VGA_AR_DATA_READ 0x3c1
-#define VGA_GR_INDEX 0x3ce
-#define VGA_GR_DATA 0x3cf
+#define VGA_GR_INDEX 0x3ce
+#define VGA_GR_DATA 0x3cf
/* GR05 */
-#define VGA_GR_MEM_READ_MODE_SHIFT 3
-#define VGA_GR_MEM_READ_MODE_PLANE 1
+#define VGA_GR_MEM_READ_MODE_SHIFT 3
+#define VGA_GR_MEM_READ_MODE_PLANE 1
/* GR06 */
-#define VGA_GR_MEM_MODE_MASK 0xc
-#define VGA_GR_MEM_MODE_SHIFT 2
-#define VGA_GR_MEM_A0000_AFFFF 0
-#define VGA_GR_MEM_A0000_BFFFF 1
-#define VGA_GR_MEM_B0000_B7FFF 2
-#define VGA_GR_MEM_B0000_BFFFF 3
+#define VGA_GR_MEM_MODE_MASK 0xc
+#define VGA_GR_MEM_MODE_SHIFT 2
+#define VGA_GR_MEM_A0000_AFFFF 0
+#define VGA_GR_MEM_A0000_BFFFF 1
+#define VGA_GR_MEM_B0000_B7FFF 2
+#define VGA_GR_MEM_B0000_BFFFF 3
#define VGA_DACMASK 0x3c6
#define VGA_DACRX 0x3c7
@@ -3701,20 +3701,20 @@
#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
/* IVB */
-#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
-#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
-#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
-#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
-#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
-#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
-#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
+#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
+#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
+#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
+#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
+#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
+#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
+#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 << 22)
/* legacy values */
-#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
-#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
-#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
-#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
-#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
+#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
+#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
+#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
+#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
+#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
diff --git a/src/mainboard/lenovo/x60/i915io.c b/src/mainboard/lenovo/x60/i915io.c
index 9b21094a3b..355286786a 100644
--- a/src/mainboard/lenovo/x60/i915io.c
+++ b/src/mainboard/lenovo/x60/i915io.c
@@ -21,7 +21,7 @@
#include "i915io.h"
struct iodef iodefs[] = {
-{V,0,},
+{V, 0,},
{M, 1, "Linux agpgart interface v0.103", 0x0, 0x0, 0},
{M, 1, "agpgart-intel 0000:00:00.0:Intel 945GM Chipset", 0x0, 0x0, 0},
{M, 1, "agpgart-intel 0000:00:00.0:detected gtt size:262144K total, 262144K mappable", 0x0, 0x0, 0},
@@ -36,7 +36,7 @@ struct iodef iodefs[] = {
{R, 1, "", PP_OFF_DELAYS, 0x00000000, 0},
{W, 1, "", PP_ON_DELAYS, 0x00000000, 0},
{W, 1, "", PP_OFF_DELAYS, 0x00000000, 0},
-{W, 1, "", INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE |0x08000800, 0},
+{W, 1, "", INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE | 0x08000800, 0},
{W, 1, "", RENDER_RING_BASE, 0x00000000, 0},
{W, 1, "", RENDER_RING_BASE+0x4, 0x00000000, 0},
{W, 1, "", RENDER_RING_BASE+0x8, 0x00000000, 0},
@@ -53,13 +53,13 @@ struct iodef iodefs[] = {
{W, 1, "", FENCE_REG_965_0+0x14, 0x00000000, 0},
{W, 1, "", FENCE_REG_965_0+0x18, 0x00000000, 0},
{W, 1, "", FENCE_REG_965_0+0x1c, 0x00000000, 0},
-{R, 1, "", DCC, DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED | DCC_CHANNEL_XOR_BIT_17 |0x000f0202, 0},
+{R, 1, "", DCC, DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED | DCC_CHANNEL_XOR_BIT_17 | 0x000f0202, 0},
{M, 1, "[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).", 0x0, 0x0, 0},
{M, 1, "[drm] Driver supports precise vblank timestamp query.", 0x0, 0x0, 0},
{M, 1, "i915 0000:00:02.0:Invalid ROM contents", 0x0, 0x0, 0},
{M, 1, "[drm] failed to find VBIOS tables", 0x0, 0x0, 0},
{M, 1, "vgaarb:device changed decodes:PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem", 0x0, 0x0, 0},
-{W, 1, "", VGACNTRL, VGA_DISP_DISABLE |0x80000000, 0},
+{W, 1, "", VGACNTRL, VGA_DISP_DISABLE | 0x80000000, 0},
{R, 1, "", PFIT_CONTROL, 0x00000000, 0},
{W, 1, "", 0x5100, 0x00000003, 0},
{W, 1, "", 0x5104, 0x460100a1, 0},
@@ -202,14 +202,14 @@ struct iodef iodefs[] = {
{W, 1, "", IMR, 0xfffd73ae, 0},
{W, 1, "", IER, 0x00028053, 0},
{R, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0},
-{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0},
-{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0},
-{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000228, 0},
-{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000228, 0},
-{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0},
+{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0},
+{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0},
+{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0},
+{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0},
+{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0},
{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0},
-{W, 1, "", PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS |0x00000800, 0},
-{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0},
+{W, 1, "", PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS | 0x00000800, 0},
+{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0},
{W, 1, "", 0x5100, 0x00000002, 0},
{W, 1, "", 0x5104, 0x460100a1, 0},
{R, 2, "", 0x5108, 0x00009c00, 0},
@@ -234,21 +234,21 @@ struct iodef iodefs[] = {
{W, 1, "", _PIPEACONF, 0x00000000, 0},
{R, 1, "", _DPLL_A, 0x94020003, 0},
{R, 1, "", _PIPEACONF, 0x00000000, 0},
-{W, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000a03, 0},
-{W, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000a03, 0},
+{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
+{R, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0},
+{W, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0},
{R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 2, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 2, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{W, 1, "", _DSPBCNTR, 0x40000000, 0},
{R, 1, "", _DSPBCNTR, 0x40000000, 0},
{W, 1, "", _DSPBCNTR, 0x58000000, 0},
{W, 1, "", _DSPBSTRIDE, 0x00001400, 0},
{W, 1, "", _DSPBADDR, 0x00020000, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0},
{W, 1, "", FW_BLC, 0x011d011a, 0},
{W, 1, "", FW_BLC2, 0x00000102, 0},
{R, 1, "", TV_CTL, 0x00000000, 0},
@@ -273,7 +273,7 @@ struct iodef iodefs[] = {
{W, 1, "", TV_CSC_V2, 0x06d00200, 0},
{W, 1, "", TV_CLR_KNOBS, 0x00606000, 0},
{W, 1, "", TV_CLR_LEVEL, 0x010b00e1, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _DSPBCNTR, 0x58000000, 0},
{W, 1, "", _DSPBCNTR, 0x58000000, 0},
{R, 1, "", _DSPBADDR, 0x00020000, 0},
@@ -284,7 +284,7 @@ struct iodef iodefs[] = {
{W, 1, "", _PFA_CTL_1, 0x80000000, 0},
{W, 1, "", _PFA_WIN_POS, 0x00360024, 0},
{W, 1, "", _PFA_WIN_SZ, 0x02640198, 0},
-{W, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{W, 1, "", _DSPBCNTR, 0x58000000, 0},
{R, 1, "", _DSPBADDR, 0x00020000, 0},
{W, 1, "", _DSPBADDR, 0x00020000, 0},
@@ -497,26 +497,26 @@ struct iodef iodefs[] = {
{R, 1, "", TV_DAC, 0x70000000, 0},
{W, 1, "", TV_DAC, 0x00000000, 0},
{W, 1, "", TV_CTL, 0x000c0000, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0},
{W, 1, "", INSTPM+0x20, 0x0001002f, 0},
{W, 1, "", FW_BLC, 0x0101011a, 0},
{W, 1, "", FW_BLC2, 0x00000102, 0},
-{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK |0x80008000, 0},
+{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80008000, 0},
{R, 1, "", PP_CONTROL, 0xabcd0000, 0},
{R, 1, "", LVDS, 0x40000000, 0},
{R, 1, "", _DPLL_A, 0x94020003, 0},
{W, 3, "", _DPLL_A, 0x94020003, 0},
{R, 1, "", _DPLL_A, 0x94020003, 0},
-{R, 2, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 2, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _DSPBCNTR, 0x58000000, 0},
{W, 1, "", _DSPBCNTR, 0xd8000000, 0},
{R, 1, "", _DSPBADDR, 0x00020000, 0},
{W, 1, "", _DSPBADDR, 0x00020000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{W, 1, "", _PALETTE_A, 0x00000000, 0},
{W, 1, "", _PALETTE_A+0x4, 0x00010101, 0},
{W, 1, "", _PALETTE_A+0x8, 0x00020202, 0},
@@ -781,96 +781,96 @@ struct iodef iodefs[] = {
{R, 1, "", LVDS, 0x40000000, 0},
{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0},
{R, 1, "", TV_CTL, 0x800c0000, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 1, "", TV_DAC, 0x70000000, 0},
{R, 1, "", TV_CTL, 0x800c0000, 0},
{W, 1, "", TV_CTL, 0x000c0007, 0},
{W, 1, "", TV_DAC, 0x0f0000aa, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 1, "", TV_DAC, 0x7f0000aa, 0},
{W, 1, "", TV_DAC, 0x70000000, 0},
{W, 1, "", TV_CTL, 0x800c0000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 4, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 1, "", TV_CTL, 0x800c0000, 0},
{W, 1, "", TV_CTL, 0x000c0000, 0},
{W, 1, "", INSTPM, 0x08000800, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x62029b1b, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6217572c, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x63156af7, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x64137fac, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6510b8c6, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6607c3b5, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x661c804f, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x671a949c, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6818a96d, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6915e1d1, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6a0cec77, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6b04d273, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6c02e710, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6d00fb0c, 0},
{R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
{R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6d1b0b04, 0},
{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
@@ -878,20 +878,20 @@ struct iodef iodefs[] = {
{W, 1, "", _DSPBCNTR, 0x58000000, 0},
{R, 1, "", _DSPBADDR, 0x00020000, 0},
{W, 1, "", _DSPBADDR, 0x00020000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
{R, 1, "", _DSPACNTR, 0x00000000, 0},
{R, 1, "", _DSPBCNTR, 0x58000000, 0},
-{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0},
{W, 1, "", _PIPEACONF, 0x00000000, 0},
{R, 2, "", _PIPEADSL, 0x000003ff, 0},
{R, 1, "", _PIPEACONF, 0x00000000, 0},
{R, 1, "", _DPLL_A, 0x94020003, 0},
{W, 1, "", _DPLL_A, 0x14020003, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0},
{W, 1, "", FW_BLC, 0x011d011a, 0},
{W, 1, "", FW_BLC2, 0x00000102, 0},
{R, 1, "", _DSPBCNTR, 0x58000000, 0},
@@ -908,11 +908,11 @@ struct iodef iodefs[] = {
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{R, 2, "", LVDS, 0x40000000, 0},
{W, 1, "", _FPB0, 0x00020e09, 0},
-{W, 1, "", _FPB1, FP_M1_DIV_SHIFT | DPLLA_INPUT_BUFFER_ENABLE | VF_UNIT_CLOCK_GATE_DISABLE |0x00020e09, 0},
-{W, 1, "", _DPLL_B, DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x18046000, 0},
+{W, 1, "", _FPB1, FP_M1_DIV_SHIFT | DPLLA_INPUT_BUFFER_ENABLE | VF_UNIT_CLOCK_GATE_DISABLE | 0x00020e09, 0},
+{W, 1, "", _DPLL_B, DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x18046000, 0},
{R, 1, "", LVDS, 0x40000000, 0},
-{W, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
-{W, 2, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
+{W, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
+{W, 2, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{W, 1, "", _HTOTAL_B, 0x053f03ff, 0},
{W, 1, "", _HBLANK_B, 0x053f03ff, 0},
@@ -924,7 +924,7 @@ struct iodef iodefs[] = {
{W, 1, "", _DSPASIZE, 0x02ff03ff, 0},
{W, 1, "", _DSPASTRIDE+0x4, 0x00000000, 0},
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
-{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
+{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{W, 1, "", _PIPEBCONF, 0x80000000, 0},
{R, 1, "", _PIPEBSTAT, 0x00000040, 0},
@@ -939,21 +939,21 @@ struct iodef iodefs[] = {
{W, 1, "", _DSPACNTR, 0x59000000, 0},
{W, 1, "", _DSPASTRIDE, 0x00001000, 0},
{W, 1, "", _DSPAADDR, 0x00020000, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0},
{W, 1, "", FW_BLC, 0x011d011a, 0},
{W, 1, "", FW_BLC2, 0x00000102, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0},
{W, 1, "", INSTPM+0x20, 0x0001003f, 0},
{W, 1, "", FW_BLC, 0x011d0109, 0},
{W, 1, "", FW_BLC2, 0x00000102, 0},
-{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK |0x80008000, 0},
+{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80008000, 0},
{R, 1, "", PP_CONTROL, 0xabcd0000, 0},
-{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
-{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
-{W, 3, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
-{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
+{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
+{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
+{W, 3, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
+{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
{R, 2, "", _PIPEBCONF, 0x80000000, 0},
{R, 1, "", _DSPACNTR, 0x59000000, 0},
{W, 1, "", _DSPACNTR, 0xd9000000, 0},
@@ -1219,22 +1219,22 @@ struct iodef iodefs[] = {
{W, 1, "", 0xabf4, 0x00fdfdfd, 0},
{W, 1, "", 0xabf8, 0x00fefefe, 0},
{W, 1, "", 0xabfc, 0x00ffffff, 0},
-{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
-{W, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
+{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
+{W, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
{W, 1, "", PFIT_PGM_RATIOS, 0x00000000, 0},
-{W, 1, "", PFIT_CONTROL, ( PFIT_PIPE_SHIFT &0x8)|0x00000008, 0},
+{W, 1, "", PFIT_CONTROL, (PFIT_PIPE_SHIFT & 0x8) | 0x00000008, 0},
{R, 1, "", PP_CONTROL, 0xabcd0000, 0},
-{W, 1, "", PP_CONTROL, POWER_TARGET_ON |0xabcd0001, 0},
-{R, 1, "", PP_STATUS, PP_READY |( PP_SEQUENCE_SHIFT &0x8)|0x4000000a, 0},
-{R, 1, "", PP_STATUS, PP_ON | PP_READY | PP_SEQUENCE_POWER_UP |( PP_SEQUENCE_SHIFT &0x8)|0xd000000a, 0},
+{W, 1, "", PP_CONTROL, POWER_TARGET_ON | 0xabcd0001, 0},
+{R, 1, "", PP_STATUS, PP_READY | (PP_SEQUENCE_SHIFT & 0x8) | 0x4000000a, 0},
+{R, 1, "", PP_STATUS, PP_ON | PP_READY | PP_SEQUENCE_POWER_UP | (PP_SEQUENCE_SHIFT & 0x8) | 0xd000000a, 0},
{R, 1, "", BLC_PWM_CTL, 0x00000000, 0},
{M, 1, "i915:fixme:max PWM is zero", 0x0, 0x0, 0},
{R, 1, "", BLC_PWM_CTL, 0x00000000, 0},
{W, 1, "", BLC_PWM_CTL, 0x00000002, 0},
-{R, 2, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
+{R, 2, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0},
{R, 1, "", TV_CTL, 0x000c0000, 0},
-{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
+{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0},
{R, 1, "", TV_CTL, 0x000c0000, 0},
{R, 1, "", _PIPEACONF, 0x00000000, 0},
@@ -2270,4 +2270,4 @@ struct iodef iodefs[] = {
{0,},
};
-int niodefs = sizeof (iodefs) / sizeof (iodefs[0]);
+int niodefs = sizeof(iodefs) / sizeof(iodefs[0]);
diff --git a/src/mainboard/lenovo/x60/i915io.h b/src/mainboard/lenovo/x60/i915io.h
index 6c5fb34e71..8f37d9b21a 100644
--- a/src/mainboard/lenovo/x60/i915io.h
+++ b/src/mainboard/lenovo/x60/i915io.h
@@ -52,7 +52,7 @@
* 2 -> print IO ops
* 4 -> print the number of times we spin on a register in a poll
* 8 -> restore whatever the previous verbosity level was
- * (only one deep stack)
+ * (only one deep stack)
*
* Again, this is not really meant for human consumption. There is not a poll
* operator as such because, sometimes, there is a read/write/read where the
@@ -84,4 +84,3 @@ u32 pack_aux(u32 *src, int src_bytes);
void unpack_aux(u32 src, u32 *dst, int dst_bytes);
int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
u32 *recv, int recv_size);
-
diff --git a/src/mainboard/lenovo/x60/intel_dp.c b/src/mainboard/lenovo/x60/intel_dp.c
index 9fb66f6cb7..e48f4f81e4 100644
--- a/src/mainboard/lenovo/x60/intel_dp.c
+++ b/src/mainboard/lenovo/x60/intel_dp.c
@@ -86,10 +86,10 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
}
if (try == 3) {
- printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
- printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n",
- io_i915_READ32(ch_ctl));
- return -1;
+ printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+ printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n",
+ io_i915_READ32(ch_ctl));
+ return -1;
}
/* Must try at least 3 times according to DP spec */
@@ -140,7 +140,8 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
*/
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
- printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status);
+ printk(BIOS_SPEW,
+ "dp_aux_ch receive error status 0x%08x\n", status);
return -1;
}
@@ -164,4 +165,3 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
return recv_bytes;
}
-
diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
index b344ccb364..d425cd2128 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -40,7 +40,7 @@
#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
- unsigned int gfx);
+ unsigned int gfx);
static acpi_cstate_t cst_entries[] = {
{ 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 20e8bf3667..50e07f0740 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -56,7 +56,7 @@ static void gma_func0_init(struct device *dev)
iobase = dev->resource_list[1].base;
mmiobase = dev->resource_list[0].base;
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
- graphics_base = dev->resource_list[2].base + 0x20000 ;
+ graphics_base = dev->resource_list[2].base + 0x20000;
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
i915lightup(physbase, iobase, mmiobase, graphics_base);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 13:39:08 +0000