diff options
| -rwxr-xr-x | src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg | 89 | ||||
| -rw-r--r-- | src/mainboard/motorola/sandpoint/sp7410.cfg | 139 | ||||
| -rw-r--r-- | src/mainboard/totalimpact/briq/briQ7400.cfg | 178 |
3 files changed, 406 insertions, 0 deletions
diff --git a/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg b/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg new file mode 100755 index 0000000000..568efb8f6b --- /dev/null +++ b/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg @@ -0,0 +1,89 @@ +; bdiGDB configuration file for the Embedded Planet EP405PC +; --------------------------------------------------------- +; +[INIT] +; init core register +WSPR 954 0x00000000 ;DCWR: Disable data cache write-thru +WSPR 1018 0x00000000 ;DCCR: Disable data cache +WSPR 1019 0x00000000 ;ICCR: Disable instruction cache +WSPR 981 0x00000000 ;EVPR: Exception Vector Table @0x00000000 + +; Setup SDRAM Controller +WDCR 16 0x00000080 ;Select SDRAM0_TR +WDCR 17 0x010E8016 ;TR: SDRAM Timing Register +WDCR 16 0x00000040 ;Select SDRAM0_B0CR +WDCR 17 0x00084001 ;Select bank 0 +WDCR 16 0x00000030 ;Select SDRAM0_RTR +WDCR 17 0x08080000 ;RTR: Refresh Timing Register +WDCR 16 0x00000094 ;Select SDRAM0_ECCCFG +WDCR 17 0x00000000 ;ECC: Disabled +WDCR 16 0x00000034 ;Select SDRAM0_PMIT +WDCR 17 0x0F000000 ;PMIT: Power Management Idle Timer +DELAY 1 ;Wait for SDRAM powerup +WDCR 16 0x00000020 ;Select SDRAM0_CFG +WDCR 17 0x80C00000 ;CFG: Enable + +; MMU +WM32 0xf0 0x00000000 ;invalidate page table base + +; EBC +WDCR 0x12 0x00000004 ;Select EBC0_B4CR +WDCR 0x13 0xF4058000 ;Set NVRTC/BCSR +WDCR 0x12 0x00000014 ;Select EBC0_B4AP +WDCR 0x13 0x04050000 ;Set NVRTC/BCSR timing +WM8 0xF4000003 0x20 ;Enable UART0 +WM8 0xF4000009 0x07 ;LED +DELAY 500 +WM8 0xF4000009 0x0b ;LED +DELAY 500 +WM8 0xF4000009 0x0d ;LED +DELAY 500 +WM8 0xF4000009 0x0e ;LED +DELAY 500 + +[TARGET] +JTAGCLOCK 0 ;use 16 MHz JTAG clock +CPUTYPE 405 ;the used target CPU type +BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) +;WAKEUP 3000 ;wakeup time after reset +BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint +STEPMODE JTAG ;JTAG or HWBP, HWPB uses one or two hardware breakpoints +VECTOR CATCH ;catch unhandled exceptions +MMU XLAT 0xC0000000 ;enable virtual address mode +PTBASE 0x000000f0 ;address where kernel/user stores pointer to page table +SIO 2002 9600 ;TCP port for serial IO +;SIO 2002 115200 ;TCP port for serial IO + +;REGLIST SPR ;select register to transfer to GDB +;REGLIST ALL ;select register to transfer to GDB +;SCANPRED 2 2 ;JTAG devices connected before PPC400 +;SCANSUCC 3 3 ;JTAG devices connected after PPC400 + +[HOST] +IP 10.0.1.2 +FORMAT ELF +FILE linuxbios.elf +;START 0x200000 +LOAD MANUAL ;load code MANUAL or AUTO after reset +DEBUGPORT 2001 +DUMP dump.bin ;Linux: dump.bin must already exist and public writable + +[FLASH] +WORKSPACE 0x00004000 ;workspace in target RAM for fast programming algorithm +CHIPTYPE AM29BX16 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) +CHIPSIZE 0x400000 ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000) +BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) +ERASE 0xFFF80000 ;erase sector 0 of flash in U7 (AM29F040) +ERASE 0xFFF90000 ;erase sector 1 of flash +ERASE 0xFFFA0000 ;erase sector 2 of flash +ERASE 0xFFFB0000 ;erase sector 3 of flash +ERASE 0xFFFC0000 ;erase sector 4 of flash +ERASE 0xFFFD0000 ;erase sector 5 of flash +ERASE 0xFFFE0000 ;erase sector 6 of flash +ERASE 0xFFFF0000 ;erase sector 7 of flash + +[REGS] +IDCR1 0x010 0x011 ;MEMCFGADR and MEMCFGDATA +IDCR2 0x012 0x013 ;EBCCFGADR and EBCCFGDATA +IDCR3 0x014 0x015 ;KIAR and KIDR +FILE reg405gp.def diff --git a/src/mainboard/motorola/sandpoint/sp7410.cfg b/src/mainboard/motorola/sandpoint/sp7410.cfg new file mode 100644 index 0000000000..b5b8391ec8 --- /dev/null +++ b/src/mainboard/motorola/sandpoint/sp7410.cfg @@ -0,0 +1,139 @@ +; bdiGDB configuration file for the Sandpoint X3 evaluation system +; with the Altimus 7410 PMC +;----------------------------------------------------------------- +; +[INIT] +; init core register +WREG MSR 0x00000000 ;clear MSR +; +; init memory controller (based on DINK32) +WM32 0xFEC00000 0x46000080 ;select PCIARB +WM16 0xFEE00002 0x0080 ; +WM32 0xFEC00000 0x73000080 ;select ODCR +WM8 0xFEE00003 0xd1 ; +WM32 0xFEC00000 0x74000080 ;select CDCR +WM16 0xFEE00000 0x00fd ; +WM32 0xFEC00000 0x76000080 ;select MICR +WM8 0xFEE00002 0x40 ; +WM32 0xFEC00000 0x80000080 ;select MSAR1 +WM32 0xFEE00000 0x0080a0c0 ; +WM32 0xFEC00000 0x84000080 ;select MSAR2 +WM32 0xFEE00000 0xe0002040 ; +WM32 0xFEC00000 0x88000080 ;select MSAR3 +WM32 0xFEE00000 0x00000000 ; +WM32 0xFEC00000 0x8c000080 ;select MSAR4 +WM32 0xFEE00000 0x00010101 ; +WM32 0xFEC00000 0x90000080 ;select MEAR1 +WM32 0xFEE00000 0x7f9fbfdf ; +WM32 0xFEC00000 0x94000080 ;select MEAR2 +WM32 0xFEE00000 0xff1f3f5f ; +WM32 0xFEC00000 0x98000080 ;select MEAR3 +WM32 0xFEE00000 0x00000000 ; +WM32 0xFEC00000 0x9c000080 ;select MEAR4 +WM32 0xFEE00000 0x00010101 ; +WM32 0xFEC00000 0xa0000080 ;select MBEN +WM8 0xFEE00000 0x01 ; +WM32 0xFEC00000 0xa3000080 ;select PGMAX +WM8 0xFEE00003 0x32 ; +WM32 0xFEC00000 0xa8000080 ;select PIC1 +WM32 0xFEE00000 0x981a14ff ; +WM32 0xFEC00000 0xac000080 ;select PIC2 +WM32 0xFEE00000 0x00000004 ; +WM32 0xFEC00000 0xe0000080 ;select AMBOR +WM8 0xFEE00000 0xc0 ; +WM32 0xFEC00000 0xf0000080 ;select MCCR1 +WM32 0xFEE00000 0xaaaae075 ;do not set MEMGO +WM32 0xFEC00000 0xf4000080 ;select MCCR2 +WM32 0xFEE00000 0x2c184004 ; +WM32 0xFEC00000 0xf8000080 ;select MCCR3 +WM32 0xFEE00000 0x00003078 ; +WM32 0xFEC00000 0xfc000080 ;select MCCR4 +WM32 0xFEE00000 0x39223235 ; +DELAY 100 +WM32 0xFEC00000 0xf0000080 ;select MCCR1 +WM32 0xFEE00000 0xaaaae875 ;now set MEMGO +; +WM32 0xFEC00000 0x78000080 ;select EUMBBAR +WM32 0xFEE00000 0x000000fc ;Embedded utility memory block at 0xFC000000 +; +;WM32 0xFEC00000 0xa8000080 ;select PICR1 +;WM32 0xFEE00000 0x901014ff ;enable flash write (Flash on processor bus) + +; +; Enable UART0 +; +WM8 0xFE00015C 0x07 +WM8 0xFE00015D 0x06 +WM8 0xFE00015C 0x30 +WM8 0xFE00015D 0x00 +WM8 0xFE00015C 0x60 +WM8 0xFE00015D 0x03 +WM8 0xFE00015C 0x61 +WM8 0xFE00015D 0xf8 +WM8 0xFE00015C 0x30 +WM8 0xFE00015D 0x01 +; +; define maximal transfer size +;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM) +TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash) + + +[TARGET] +CPUTYPE 7400 ;the CPU type (603EV,750,8240,8260,7400) +JTAGCLOCK 0 ;use 16 MHz JTAG clock +WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush +BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY) +BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint +;STEPMODE HWBP ;TRACE or HWBP, HWPB uses a hardware breakpoint +;VECTOR CATCH ;catch unhandled exceptions +DCACHE NOFLUSH ;data cache flushing (FLUSH | NOFLUSH) +;PARITY ON ;enable data parity generation +MEMDELAY 400 ;additional memory access delay +;REGLIST STD ;select register to transfer to GDB +;L2PM 0x00100000 0x80000 ;L2 privat memory +;SIO 2002 115200 +SIO 2002 9600 +;MMU XLAT +;PTBASE 0x000000f0 + +[HOST] +IP 10.0.1.11 +;FILE E:\cygnus\root\usr\demo\sp7400\vxworks +FILE linuxbios.elf +FORMAT ELF +;START 0x403104 +LOAD MANUAL ;load code MANUAL or AUTO after reset +DEBUGPORT 2001 + +[FLASH] +; Am29LV800BB on local processor bus (RCS0) +; set PPMC7410 switch SW2-1 OFF => ROM on Local bus +; enable flash write in PICR1 (see INIT part) +; set maximal transfer size to 4 bytes (see INIT part) +CHIPTYPE AM29BX8 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) +CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000) +BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) +WORKSPACE 0x00000000 ;workspace in SDRAM +FILE linuxbios.elf +FORMAT ELF +ERASE 0xFFF00000 ;erase sector 0 of flash +ERASE 0xFFF04000 ;erase sector 1 of flash +ERASE 0xFFF06000 ;erase sector 2 of flash +ERASE 0xFFF08000 ;erase sector 3 of flash +ERASE 0xFFF10000 ;erase sector 4 of flash +ERASE 0xFFF20000 ;erase sector 5 of flash +ERASE 0xFFF30000 ;erase sector 6 of flash +ERASE 0xFFF40000 ;erase sector 7 of flash +ERASE 0xFFF50000 ;erase sector 8 of flash +ERASE 0xFFF60000 ;erase sector 9 of flash +ERASE 0xFFF70000 ;erase sector 10 of flash + +[REGS] +DMM1 0xFC000000 ;Embedded utility memory base address +IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0 +IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1 +IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2 +IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3 +FILE mpc107.def + + diff --git a/src/mainboard/totalimpact/briq/briQ7400.cfg b/src/mainboard/totalimpact/briq/briQ7400.cfg new file mode 100644 index 0000000000..20a438703e --- /dev/null +++ b/src/mainboard/totalimpact/briq/briQ7400.cfg @@ -0,0 +1,178 @@ +; bdiGDB configuration file for briQ (http://www.totalimpact.com) +; --------------------------------------------------------------- +; +; NOTE: As of June 2004, you will need to install a pull-down +; on the COP/JTAG QACK line. Without this, the BDI2000 +; is not able to halt the CPU +; (http://www.ultsol.com/faq-P210.htm) +; +[INIT] +; init core register +WREG MSR 0x00000000 ;clear MSR +; +; init CPC710 +; +WM32 0xFF000010 0xF0000000 ; RSTR +WM32 0xFF001020 0x00000000 ; SIOC +WM32 0xFF001000 0x00780000 ; UCTL (resID=7|TBE) +WM32 0xFF001030 0x00000000 ; ABCNTL +WM32 0xFF001040 0x00000000 ; SRST +WM32 0xFF001050 0x00000000 ; ERRC +WM32 0xFF001060 0x00000000 ; SESR +WM32 0xFF001070 0x00000000 ; SEAR +WM32 0xFF001100 0x000000E0 ; PGCHP (PReP|ARTRY|750|SYS_TEA) +WM32 0xFF001130 0x40000000 ; GPDIR +WM32 0xFF001150 0x40000000 ; GPOUT +WM32 0xFF001160 0x709C2508 ; ATAS +WM32 0xFF001170 0x00000000 ; AVDG +WM32 0xFF001220 0x00000000 ; MESR +WM32 0xFF001230 0x00000000 ; MEAR +WM32 0xFF001210 0x00000000 ; MWPR +WM32 0xFF001120 0x00000000 ; RGBAN1 +; +; init memory - this assumes 2 x 512MB DIMMs +; +WM32 0xFF001300 0x80000080 ; MCER0 +WM32 0xFF001310 0x82000080 ; MCER1 +WM32 0xFF001320 0x00000000 ; MCER2 +WM32 0xFF001330 0x00000000 ; MCER3 +WM32 0xFF001340 0x00000000 ; MCER4 +WM32 0xFF001350 0x00000000 ; MCER5 +WM32 0xFF001200 0xD2B06000 ; MCCR +DELAY 1000 +; +; enable pci +; +WM32 0xFF00000C 0x80000002 ; CNFR +WM32 0xFF200018 0xFF500000 ; PCIBAR +WM32 0xFF201000 0x80000000 ; PCIENB +WM32 0xFF00000C 0x00000000 ; CNFR +; +; config pci +; +WM32 0xFF5F8000 0x06000080 +WM16 0xFF5F8010 0xFFFF +WM32 0xFF5F8000 0x40000080 +WM16 0xFF5F8010 0x0000 +WM32 0xFF5F6120 0x40000000 ; PCIDG +WM32 0xFF5F7800 0x00000000 ; PIBAR +WM32 0xFF5F7810 0x00000000 ; PMBAR +WM32 0xFF5F7F20 0xA000C000 ; PR +WM32 0xFF5F7F30 0xFC000000 ; ACR +WM32 0xFF5F7F40 0xF8000000 ; MSIZE +WM32 0xFF5F7F60 0xF8000000 ; IOSIZE +WM32 0xFF5F7F80 0xC0000000 ; SMBAR +WM32 0xFF5F7FC0 0x80000000 ; SIBAR +WM32 0xFF5F8100 0x00000080 ; PSSIZE +WM32 0xFF5F8120 0x00000000 ; BARPS +WM32 0xFF5F8140 0x00000080 ; PSBAR +WM32 0xFF5F8200 0x00000000 ; BPMDLK +WM32 0xFF5F8210 0x00000000 ; TPMDLK +WM32 0xFF5F8220 0x00000000 ; BIODLK +WM32 0xFF5F8230 0x00000000 ; TIODLK +WM32 0xFF5F8000 0x04000080 +WM16 0xFF5F8010 0xA7FD +WM32 0xFF5F7EF0 0xFC000000 ; CRR +; +; VFD - output the sequence '01234' to show +; something is happening +; +;WM8 0x80000390 0x38 +;WM8 0x80000390 0x01 +;WM8 0x80000390 0x0C +;WM8 0x80000390 0x06 +;WM8 0x80000390 0x02 +;DELAY 100 +;WM8 0x80000391 0x30 +;DELAY 100 +;WM8 0x80000391 0x31 +;DELAY 100 +;WM8 0x80000391 0x32 +;DELAY 100 +;WM8 0x80000391 0x33 +;DELAY 100 +;WM8 0x80000391 0x34 +; +; UART - output the sequence '01234' to show +; something is happening +; +WM8 0x800003F9 0 +WM8 0x800003FA 1 +WM8 0x800003FB 0x83 +WM8 0x800003F8 4 ; 115200 +WM8 0x800003F9 0 +WM8 0x800003FB 0x3 +DELAY 100 +WM8 0x800003F8 0x30 +DELAY 100 +WM8 0x800003F8 0x31 +DELAY 100 +WM8 0x800003F8 0x32 +DELAY 100 +WM8 0x800003F8 0x33 +DELAY 100 +WM8 0x800003F8 0x34 +; +; define maximal transfer size +;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM) +TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash) + + +[TARGET] +CPUTYPE 7400 ;the CPU type (603EV,750,8240,8260,7400) +JTAGCLOCK 0 ;use 16 MHz JTAG clock +WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush +BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY) +BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint +STEPMODE TRACE ;TRACE or HWBP, HWPB uses a hardware breakpoint +;VECTOR CATCH ;catch unhandled exceptions +DCACHE FLUSH ;data cache flushing (FLUSH | NOFLUSH) +;PARITY ON ;enable data parity generation +;MEMDELAY 4000 ;additional memory access delay +;REGLIST STD ;select register to transfer to GDB +;L2PM 0x00100000 0x80000 ;L2 privat memory +BOOTADDR 0xfff00100 +STARTUP RESET + +[HOST] +FORMAT ELF +LOAD MANUAL ;load code MANUAL or AUTO after reset +DEBUGPORT 2001 + +[FLASH] +; Am29LV800BB on local processor bus (RCS0) +; set PPMC7410 switch SW2-1 OFF => ROM on Local bus +; enable flash write in PICR1 (see INIT part) +; set maximal transfer size to 4 bytes (see INIT part) +CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) +CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000) +BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) +;WORKSPACE 0x00000000 ;workspace in SDRAM +FILE linuxbios.rom +FORMAT ELF +ERASE 0xFFF00000 ;erase sector 0 of flash +ERASE 0xFFF10000 ;erase sector 1 of flash +ERASE 0xFFF20000 ;erase sector 2 of flash +ERASE 0xFFF30000 ;erase sector 3 of flash +ERASE 0xFFF40000 ;erase sector 4 of flash +ERASE 0xFFF50000 ;erase sector 5 of flash +ERASE 0xFFF60000 ;erase sector 6 of flash +ERASE 0xFFF70000 ;erase sector 7 of flash +;ERASE 0xFFF80000 ;erase sector 8 of flash +;ERASE 0xFFF90000 ;erase sector 9 of flash +;ERASE 0xFFFA0000 ;erase sector 10 of flash +;ERASE 0xFFFB0000 ;erase sector 11 of flash +;ERASE 0xFFFC0000 ;erase sector 12 of flash +;ERASE 0xFFFD0000 ;erase sector 13 of flash +;ERASE 0xFFFE0000 ;erase sector 14 of flash +;ERASE 0xFFFF0000 ;erase sector 15 of flash + +[REGS] +;DMM1 0xFC000000 ;Embedded utility memory base address +;IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0 +;IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1 +;IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2 +;IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3 +FILE cpc700.def + + |