diff options
32 files changed, 45 insertions, 161 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 19eb041eac..1b6f62c351 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -19,9 +19,9 @@ #include <commonlib/helpers.h> #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <fsp/car.h> #include <fsp/util.h> -#include <fsp/memmap.h> #include <program_loading.h> /* platform_enter_postcar() determines the stack to use after diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h deleted file mode 100644 index 3f3850f3f5..0000000000 --- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _COMMON_MEMMAP_H_ -#define _COMMON_MEMMAP_H_ - -#include <types.h> - -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - -#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 21f4ab9b05..2f53957596 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -19,7 +19,7 @@ #include <cf9_reset.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <fsp/romstage.h> #include <fsp/util.h> #include <lib.h> /* hexdump */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 52a886ce30..049dfd05f0 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -17,7 +17,7 @@ #include <bootmode.h> #include <arch/acpi.h> #include <console/console.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <fsp/ramstage.h> #include <fsp/util.h> #include <lib.h> diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c index 2d594e6048..ab0c1c0126 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/drivers/intel/fsp1_1/stage_cache.c @@ -15,7 +15,7 @@ */ #include <console/console.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <stage_cache.h> void stage_cache_external_region(void **base, size_t *size) diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h deleted file mode 100644 index 3f3850f3f5..0000000000 --- a/src/drivers/intel/fsp2_0/include/fsp/memmap.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _COMMON_MEMMAP_H_ -#define _COMMON_MEMMAP_H_ - -#include <types.h> - -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - -#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 3071106080..edd1be8588 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -583,4 +583,26 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); void *backup_default_smm_area(void); void restore_default_smm_area(void *smm_save_area); +/* + * Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. + */ +void smm_region(void **start, size_t *size); +void smm_region_info(void **start, size_t *size); + +enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* Fills in the start and size for the requested SMM subregion. Returns + * 0 on success, < 0 on failure. */ +int smm_subregion(int sub, void **start, size_t *size); + #endif /* CPU_X86_SMM_H */ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index bee2b4b49f..84f4729b20 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -18,6 +18,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <device/device.h> diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 65705b93f3..57373c9a08 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -99,29 +99,8 @@ #define NB_CAPABILITIES2 0x84 #define CMP_CAP_MASK 0xff -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - void amd_initcpuio(void); -/* - * Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. - */ -void smm_region_info(void **start, size_t *size); -/* - * Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. - */ -int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c index 7c855bb1e1..8eb2e39883 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/picasso/ramtop.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 950b41f5a3..458886d70c 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -19,6 +19,7 @@ #include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index f751dc8046..9961153b0b 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -18,6 +18,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <device/device.h> diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 60a6ea22bb..a0d7ce88dd 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -99,27 +99,6 @@ #define NB_CAPABILITIES2 0x84 #define CMP_CAP_MASK 0xff -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* - * Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. - */ -void smm_region_info(void **start, size_t *size); -/* - * Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. - */ -int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 7c855bb1e1..8eb2e39883 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 000d100fa3..4f38dbf138 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -19,6 +19,7 @@ #include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 625d956ea7..f3aa40c1a3 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -29,10 +29,10 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> -#include <fsp/memmap.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 66f4dda02d..a4101b7446 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -18,8 +18,8 @@ #include <assert.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <device/pci.h> -#include <fsp/memmap.h> #include <intelblocks/smm.h> #include <soc/systemagent.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7b10222b4b..97e2f83bdd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -27,10 +27,10 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/pae.h> #include <delay.h> +#include <cpu/x86/smm.h> #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> -#include <fsp/memmap.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 5f86a11db1..bde4b1c418 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -26,7 +26,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <fsp/memmap.h> #include <reg_script.h> #include <soc/iosf.h> #include <soc/msr.h> diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index a4692ceb65..69bbe58727 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -15,7 +15,7 @@ */ #include <cbmem.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/iosf.h> #include <soc/smm.h> diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 9267448697..e37e0d6e7d 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -21,8 +21,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <fsp/memmap.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/smm.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index c0ab82f0b7..bf58b9c12c 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -19,7 +19,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h index c04ec46800..25ff8f4ec9 100644 --- a/src/soc/intel/common/block/include/intelblocks/smm.h +++ b/src/soc/intel/common/block/include/intelblocks/smm.h @@ -32,7 +32,5 @@ */ void smm_southbridge_clear_state(void); void smm_southbridge_enable(uint16_t pm1_events); -/* API to get SMM region start and size based on Host Bridge register */ -void smm_region_info(void **start, size_t *size); #endif diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index a2a7c164c8..8ccd13a46e 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -18,7 +18,6 @@ #include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <fsp/memmap.h> #include <intelblocks/pmclib.h> #include <intelblocks/smm.h> #include <intelblocks/systemagent.h> diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index fc1024afa7..d6ddcc0548 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -21,6 +21,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/intel/turbo.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index ca01cf8def..a020891dd5 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -24,25 +24,6 @@ struct smm_relocation_attrs { uint32_t smrr_mask; }; -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> void southcluster_smm_clear_state(void); diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 256192261d..d94d1f3ddd 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -16,12 +16,12 @@ #include <cbmem.h> #include <assert.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> -#include <soc/smm.h> #include <lib.h> /* Returns base of requested region encoded in the system agent. */ diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2ad78a02df..6950620a87 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -20,6 +20,7 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <soc/fiamux.h> #include <device/mmio.h> @@ -29,7 +30,6 @@ #include <soc/pmc.h> #include <soc/romstage.h> #include <soc/smbus.h> -#include <soc/smm.h> #include <soc/soc_util.h> #include <soc/hob_mem.h> diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 991c593f72..75cb4eae3c 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -18,7 +18,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 0c5e9766c0..1000ce830c 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -19,7 +19,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <intelblocks/smihandler.h> #include <soc/gpio.h> diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 7a39b6748a..f69a88b30f 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -18,9 +18,9 @@ #include <device/mmio.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/memmap.h> #include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/msr.h> diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index bb86c6300d..b3781e2a65 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -18,11 +18,11 @@ #include <assert.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> #include <fsp/util.h> -#include <fsp/memmap.h> #include <intelblocks/pmclib.h> #include <memory_info.h> #include <smbios.h> |