diff options
| -rw-r--r-- | src/cpu/amd/car/disable_cache_as_ram.c | 23 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 12 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/init_cpus.c | 4 | ||||
| -rw-r--r-- | src/include/cpu/amd/car.h | 3 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/amdfam10.h | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/raminit.h | 1 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.h | 2 |
10 files changed, 27 insertions, 26 deletions
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index a8ff1cc17a..af5a2e985d 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -33,7 +33,7 @@ static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void) } static inline __attribute__((always_inline)) -void disable_cache_as_ram(uint8_t skip_sharedc_config) +void disable_cache_as_ram_real(uint8_t skip_sharedc_config) { msr_t msr; uint32_t family; @@ -45,15 +45,13 @@ void disable_cache_as_ram(uint8_t skip_sharedc_config) msr.lo = 0; msr.hi = 0; wrmsr(MTRR_FIX_4K_C8000, msr); -#if CONFIG_DCACHE_RAM_SIZE > 0x8000 - wrmsr(MTRR_FIX_4K_C0000, msr); -#endif -#if CONFIG_DCACHE_RAM_SIZE > 0x10000 - wrmsr(MTRR_FIX_4K_D0000, msr); -#endif -#if CONFIG_DCACHE_RAM_SIZE > 0x18000 - wrmsr(MTRR_FIX_4K_D8000, msr); -#endif + if (CONFIG_DCACHE_RAM_SIZE > 0x8000) + wrmsr(MTRR_FIX_4K_C0000, msr); + if (CONFIG_DCACHE_RAM_SIZE > 0x10000) + wrmsr(MTRR_FIX_4K_D0000, msr); + if (CONFIG_DCACHE_RAM_SIZE > 0x18000) + wrmsr(MTRR_FIX_4K_D8000, msr); + /* disable fixed mtrr from now on, * it will be enabled by ramstage again */ @@ -110,8 +108,3 @@ void disable_cache_as_ram(uint8_t skip_sharedc_config) } #endif } - -static void disable_cache_as_ram_bsp(void) -{ - disable_cache_as_ram(0); -} diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 064222a454..c647254c70 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -26,9 +26,17 @@ #include <cpu/amd/msr.h> #include <arch/acpi.h> #include <romstage_handoff.h> -#include "cbmem.h" +#include <cbmem.h> + #include "cpu/amd/car/disable_cache_as_ram.c" +// For set_sysinfo_in_ram() +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8) +#include "northbridge/amd/amdk8/raminit.h" +#else +#include "northbridge/amd/amdfam10/raminit.h" +#endif + #if CONFIG_RAMTOP <= 0x100000 #error "You need to set CONFIG_RAMTOP greater than 1M" #endif @@ -171,7 +179,7 @@ void post_cache_as_ram(void) void cache_as_ram_new_stack(void) { print_car_debug("Disabling cache as RAM now\n"); - disable_cache_as_ram_bsp(); + disable_cache_as_ram_real(0); // inline disable_cache(); /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index c540320bfb..2ed76e1e1f 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -1,4 +1,5 @@ romstage-y += ../../x86/mtrr/earlymtrr.c +romstage-y += ../car/post_cache_as_ram.c romstage-y += init_cpus.c diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index f5a949cede..0ecd040253 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -34,7 +34,7 @@ #include <southbridge/amd/sb800/sb800.h> #endif -#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/car/disable_cache_as_ram.c" #if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) static void set_EnableCf8ExtCfg(void) @@ -353,7 +353,7 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid) } } - disable_cache_as_ram(skip_sharedc_config); // inline + disable_cache_as_ram_real(skip_sharedc_config); // inline /* Mark the core as sleeping */ lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_ASLEEP); diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index 4d8153a153..4e89f40d3e 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -1,4 +1,5 @@ romstage-y += ../../x86/mtrr/earlymtrr.c +romstage-y += ../car/post_cache_as_ram.c # no conditionals here. If you include this file from a socket, then you get all the binaries. ramstage-y += model_fxx_init.c diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 6aff4b0c62..dae489b34f 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -15,7 +15,7 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/mtrr.h> #include <northbridge/amd/amdk8/amdk8.h> -#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/car/disable_cache_as_ram.c" #if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" @@ -220,7 +220,7 @@ static void enable_apic_ext_id(u32 node) static void STOP_CAR_AND_CPU(void) { - disable_cache_as_ram(0); // inline + disable_cache_as_ram_real(0); // inline /* stop all cores except node0/core0 the bsp .... */ stop_this_cpu(); } diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 16dacc0cdf..c4d92d93d0 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -9,10 +9,7 @@ void post_cache_as_ram(void); void cache_as_ram_switch_stack(void *stacktop); void cache_as_ram_new_stack(void); -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA) || IS_ENABLED(CONFIG_CPU_AMD_PI) || \ - IS_ENABLED(CONFIG_SOC_AMD_PI) void disable_cache_as_ram(void); -#endif void asmlinkage early_all_cores(void); diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index e9f714a62e..3e34a25ae8 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1027,6 +1027,4 @@ unsigned long northbridge_write_acpi_tables(device_t device, void northbridge_acpi_write_vars(device_t device); #endif -void set_sysinfo_in_ram(u32 val); - #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 2f9c7bafd6..029fa0e32a 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -27,6 +27,7 @@ struct MCTStatStruc; int mctRead_SPD(u32 smaddr, u32 reg); void mctSMBhub_Init(u32 node); void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); +void set_sysinfo_in_ram(u32 val); void raminit_amdmct(struct sys_info *sysinfo); void amdmct_cbmem_store_info(struct sys_info *sysinfo); void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr); diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 8b0bf93f76..d068a445f6 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -1,6 +1,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <arch/io.h> + #define NODE_ID 0x60 #define HT_INIT_CONTROL 0x6c |