diff options
| -rw-r--r-- | src/cpu/samsung/exynos5-common/exynos-fb.c | 11 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5-common/s5p-dp-core.h | 2 | ||||
| -rw-r--r-- | src/mainboard/google/snow/ramstage.c | 20 |
3 files changed, 15 insertions, 18 deletions
diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index b57e27631f..11d666b060 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -505,7 +505,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* * Initialize DP display */ -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +int dp_controller_init(struct s5p_dp_device *dp_device) { int ret; struct s5p_dp_device *dp = dp_device; @@ -561,15 +561,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) return ret; } - /* - * This delay is T3 in the LCD timing spec (defined as >200ms). We set - * this down to 60ms since that's the approximate maximum amount of time - * it'll take a bridge to start outputting LVDS data. The delay of - * >200ms is just a conservative value to avoid turning on the backlight - * when there's random LCD data on the screen. Shaving 140ms off the - * boot is an acceptable trade-off. - */ - *wait_ms = 60; return 0; } diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 2988d5d248..4df848d0ea 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -252,6 +252,6 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int dp_controller_init(struct s5p_dp_device *dp_device); int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* _S5P_DP_CORE_H */ diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index ad0266b621..962c79b653 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -139,6 +139,16 @@ static void exynos_dp_reset(void) udelay(300 * 1000); } +/* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ +#define LCD_T3_DELAY_MS 60 + #define LCD_T5_DELAY_MS 10 #define LCD_T6_DELAY_MS 10 @@ -199,7 +209,6 @@ static struct video_info snow_dp_video_info = { static void mainboard_init(device_t dev) { int dp_tries; - unsigned int wait_ms; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &snow_dp_video_info, @@ -215,20 +224,17 @@ static void mainboard_init(device_t dev) exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { - if (wait_ms) { - udelay(wait_ms); - wait_ms = 0; - } - exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } - if (dp_controller_init(&dp_device, &wait_ms)) + if (dp_controller_init(&dp_device)) continue; + udelay(LCD_T3_DELAY_MS * 1000); + snow_backlight_vdd(); snow_backlight_pwm(); snow_backlight_en(); |