4 files changed, 0 insertions, 83 deletions
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index e6a318ae8b..bec3637033 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -111,9 +111,6 @@
 #error Bad ttyS0 baud rate
 #endif
 
-/* Line Control Settings */
-#define UART_LCS	CONFIG_TTYS0_LCS
-
 #if CONFIG_CONSOLE_SERIAL8250
 unsigned char uart8250_rx_byte(unsigned base_port);
 int uart8250_can_rx_byte(unsigned base_port);
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index 8420523dce..8d1473d966 100644
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -76,18 +76,6 @@ config RAMBASE
 	hex
 	default 0x200000
 
-config TTYS0_BAUD
-	int
-	default 115200
-
-config TTYS0_BASE
-	hex
-	default 0x3f8
-
-config TTYS0_LCS
-	int
-	default 3
-
 config DEFAULT_CONSOLE_LOGLEVEL
 	int
 	default 9
@@ -96,10 +84,6 @@ config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 	bool
 	default y
 
-config CONSOLE_SERIAL8250
-	bool
-	default y
-
 config USBDEBUG
 	bool
 	default n
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index fc7f3c52cc..1027659d5c 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -20,38 +20,6 @@
 
 #include <arch/io.h>
 
-#if CONFIG_CONSOLE_POST
-
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
-#ifndef CONFIG_TTYS0_DIV
-#if ((115200%CONFIG_TTYS0_BAUD) != 0)
-#error Bad ttys0 baud rate
-#endif
-#define CONFIG_TTYS0_DIV	(115200/CONFIG_TTYS0_BAUD)
-#endif // CONFIG_TTYS0_DIV
-
-#define UART_LCS	CONFIG_TTYS0_LCS
-
-#endif // CONFIG_CONSOLE_POST == 1
-
-
 static void sb700_enable_rom(void)
 {
 	u32 word;
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index 106f664738..9108a8bb75 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -19,38 +19,6 @@
 
 #include <arch/io.h>
 
-#if CONFIG_CONSOLE_POST
-
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
-#ifndef CONFIG_TTYS0_DIV
-#if ((115200%CONFIG_TTYS0_BAUD) != 0)
-#error Bad ttys0 baud rate
-#endif
-#define CONFIG_TTYS0_DIV	(115200/CONFIG_TTYS0_BAUD)
-#endif // CONFIG_TTYS0_DIV
-
-#define UART_LCS	CONFIG_TTYS0_LCS
-
-#endif // CONFIG_CONSOLE_POST == 1
-
-
 static void sb900_enable_rom(void)
 {
   u32 word;