diff options
| -rw-r--r-- | src/soc/intel/skylake/acpi/pci_irqs.asl | 88 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 282 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/interrupt.h | 50 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/irq.h | 68 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pci_devs.h | 16 |
6 files changed, 466 insertions, 45 deletions
diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl index 3bf5f3e442..1ab6d3efb0 100644 --- a/src/soc/intel/skylake/acpi/pci_irqs.asl +++ b/src/soc/intel/skylake/acpi/pci_irqs.asl @@ -19,66 +19,64 @@ * Foundation, Inc. */ +#include <soc/interrupt.h> +#include <soc/irq.h> + Name (PICP, Package () { /* D31: cAVS, SMBus, GbE, Nothpeak */ - Package () { 0x001FFFFF, 0, 0, 16 }, - Package () { 0x001FFFFF, 1, 0, 17 }, - Package () { 0x001FFFFF, 2, 0, 18 }, - Package () { 0x001FFFFF, 3, 0, 19 }, + Package () { 0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, + Package () { 0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, + Package () { 0x001FFFFF, 2, 0, GbE_INTC_IRQ }, + Package () { 0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, /* D30: SerialIo and SCS */ - Package () { 0x001EFFFF, 0, 0, 20 }, - Package () { 0x001EFFFF, 1, 0, 21 }, - Package () { 0x001EFFFF, 2, 0, 22 }, - Package () { 0x001EFFFF, 3, 0, 23 }, + Package () { 0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package () { 0x001EFFFF, 1, 0, eMMC_IRQ }, + Package () { 0x001EFFFF, 2, 0, SDIO_IRQ }, + Package () { 0x001EFFFF, 3, 0, SD_IRQ }, /* D29: PCI Express Port 9-16 */ - Package () { 0x001DFFFF, 0, 0, 16 }, - Package () { 0x001DFFFF, 1, 0, 17 }, - Package () { 0x001DFFFF, 2, 0, 18 }, - Package () { 0x001DFFFF, 3, 0, 19 }, + Package () { 0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package () { 0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package () { 0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package () { 0x001DFFFF, 3, 0, PCIE_12_IRQ }, /* D28: PCI Express Port 1-8 */ - Package () { 0x001CFFFF, 0, 0, 16 }, - Package () { 0x001CFFFF, 1, 0, 17 }, - Package () { 0x001CFFFF, 2, 0, 18 }, - Package () { 0x001CFFFF, 3, 0, 19 }, - /* D27: PCI Express Port 17-20 */ - Package () { 0x001BFFFF, 0, 0, 16 }, - Package () { 0x001BFFFF, 1, 0, 17 }, - Package () { 0x001BFFFF, 2, 0, 18 }, - Package () { 0x001BFFFF, 3, 0, 19 }, + Package () { 0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package () { 0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package () { 0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package () { 0x001CFFFF, 3, 0, PCIE_4_IRQ }, /* D25: SerialIo */ - Package () { 0x0019FFFF, 0, 0, 32 }, - Package () { 0x0019FFFF, 1, 0, 33 }, - Package () { 0x0019FFFF, 2, 0, 34 }, + Package () { 0x0019FFFF, 0, 0, LPSS_UART2_IRQ }, + Package () { 0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package () { 0x0019FFFF, 2, 0, LPSS_I2C4_IRQ }, /* D22: CSME (HECI, IDE-R, KT redirection */ - Package () { 0x0016FFFF, 0, 0, 16 }, - Package () { 0x0016FFFF, 1, 0, 17 }, - Package () { 0x0016FFFF, 2, 0, 18 }, - Package () { 0x0016FFFF, 3, 0, 19 }, + Package () { 0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package () { 0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package () { 0x0016FFFF, 2, 0, IDER_IRQ }, + Package () { 0x0016FFFF, 3, 0, KT_IRQ }, /* D21: SerialIo */ - Package () { 0x0015FFFF, 0, 0, 16 }, - Package () { 0x0015FFFF, 1, 0, 17 }, - Package () { 0x0015FFFF, 2, 0, 18 }, - Package () { 0x0015FFFF, 3, 0, 19 }, + Package () { 0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package () { 0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package () { 0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package () { 0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, /* D20: xHCI, OTG, Thermal, Camera */ - Package () { 0x0014FFFF, 0, 0, 16 }, - Package () { 0x0014FFFF, 1, 0, 17 }, - Package () { 0x0014FFFF, 2, 0, 18 }, - Package () { 0x0014FFFF, 3, 0, 19 }, + Package () { 0x0014FFFF, 0, 0, XHCI_IRQ }, + Package () { 0x0014FFFF, 1, 0, OTG_IRQ }, + Package () { 0x0014FFFF, 2, 0, THRMAL_IRQ }, + Package () { 0x0014FFFF, 3, 0, CIO_INTD_IRQ }, /* D19: Integrated Sensor Hub */ - Package () { 0x0013FFFF, 0, 0, 20 }, + Package () { 0x0013FFFF, 0, 0, ISH_IRQ }, /* P.E.G. Root Port D1F0 */ - Package () { 0x0001FFFF, 0, 0, 16 }, - Package () { 0x0001FFFF, 1, 0, 17 }, - Package () { 0x0001FFFF, 2, 0, 18 }, - Package () { 0x0001FFFF, 3, 0, 19 }, + Package () { 0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, + Package () { 0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ }, + Package () { 0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ }, + Package () { 0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ }, /* SA IGFX Device */ - Package () { 0x0002FFFF, 0, 0, 16 }, + Package () { 0x0002FFFF, 0, 0, IGFX_IRQ }, /* SA Thermal Device */ - Package () { 0x0004FFFF, 0, 0, 16 }, + Package () { 0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, /* SA SkyCam Device */ - Package () { 0x0005FFFF, 0, 0, 16 }, + Package () { 0x0005FFFF, 0, 0, SKYCAM_IRQ }, /* SA GMM Device */ - Package () { 0x0008FFFF, 0, 0, 16 }, + Package () { 0x0008FFFF, 0, 0, GMM_IRQ }, }) Name (PICN, Package () { diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 25235c910c..51dcbd32c8 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -24,10 +24,207 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/util.h> +#include <soc/interrupt.h> +#include <soc/irq.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> +static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { + /* + * cAVS(Audio, Voice, Speach), INTA is default, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + /* + * SMBus Controller, no default value, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + /* TraceHub, INTA is default, RO register */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), + /* + * SerialIo: UART #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[7] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), + /* + * SerialIo: UART #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[8] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), + /* + * SerialIo: SPI #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[10] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), + /* + * SerialIo: SPI #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[11] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + /* SCS: eMMC (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + /* SCS: SDIO (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + /* SCS: SDCard (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + /* PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), + /* PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), + /* PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), + /* PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + /* + * PCI Express Port 1, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + /* + * PCI Express Port 2, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + /* + * PCI Express Port 3, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + /* + * PCI Express Port 4, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + /* + * PCI Express Port 5, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + /* + * PCI Express Port 6, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + /* + * PCI Express Port 7, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + /* + * PCI Express Port 8, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + /* + * SerialIo UART Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[9] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + /* + * SerialIo UART Controller #5, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[6] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + /* + * SerialIo UART Controller #4, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[5] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + /* + * SATA Controller, INTA is default, + * programmed in PciCfgSpace + 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, + PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + /* CSME: HECI #1 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME), int_A, HECI_1_IRQ), + /* CSME: HECI #2 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_2), int_B, HECI_2_IRQ), + /* CSME: IDE-Redirection (IDE-R) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_IDER), int_C, IDER_IRQ), + /* CSME: Keyboard and Text (KT) Redirection */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_KT), int_D, KT_IRQ), + /* CSME: HECI #3 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_3), int_A, HECI_3_IRQ), + /* + * SerialIo I2C Controller #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[1] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + /* + * SerialIo I2C Controller #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[2] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + /* + * SerialIo I2C Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[3] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + /* + * SerialIo I2C Controller #3, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[4] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + /* + * USB 3.0 xHCI Controller, no default value, + * programmed in PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + /* USB Device Controller (OTG) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + /* Thermal Subsystem */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THRMAL_IRQ), + /* Camera IO Host Controller */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + /* Integrated Sensor Hub */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, + PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) +}; + static void pci_domain_set_resources(device_t dev) { assign_resources(dev->link_list); @@ -72,6 +269,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) { const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; + u8 irq_config[PCH_MAX_IRQ_CONFIG]; + int i; + int intdeventry; memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); @@ -118,6 +318,49 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) /* Show SPI controller if enabled in devicetree.cb */ dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; + + /* Get Device Int Count */ + intdeventry = ARRAY_SIZE(devintconfig); + /*update irq table*/ + memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)(params->DevIntConfigPtr), devintconfig, + intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); + + params->NumOfDevIntConfig = intdeventry; + /* PxRC to IRQ programing */ + for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { + switch(i) { + case PCH_PARC: + case PCH_PCRC: + case PCH_PDRC: + case PCH_PERC: + case PCH_PFRC: + case PCH_PGRC: + case PCH_PHRC: + irq_config[i] = PCH_IRQ11; + break; + case PCH_PBRC: + irq_config[PCH_PBRC] = PCH_IRQ10; + break; + } + } + memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); + /* GPIO IRQ Route The valid values is 14 or 15*/ + if(config->GpioIrqSelect == 0) + params->GpioIrqRoute = GPIO_IRQ14; + else + params->GpioIrqRoute = config->GpioIrqSelect; + /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ + if(config->SciIrqSelect == 0) + params->SciIrqSelect = SCI_IRQ9; + else + params->SciIrqSelect = config->SciIrqSelect; + /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/ + if(config->TcoIrqSelect == 0) + params->TcoIrqSelect = TCO_IRQ9; + else + params->TcoIrqSelect = config->TcoIrqSelect; + /* TCO Irq enable/disable */ + params->TcoIrqEnable = config->TcoIrqEnable; } void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, @@ -286,6 +529,45 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, params->EnableSata); soc_display_upd_value("SataMode", 1, original->SataMode, params->SataMode); + soc_display_upd_value("NumOfDevIntConfig", 1, + original->NumOfDevIntConfig, + params->NumOfDevIntConfig); + soc_display_upd_value("PxRcConfig[PARC]", 1, + original->PxRcConfig[PCH_PARC], + params->PxRcConfig[PCH_PARC]); + soc_display_upd_value("PxRcConfig[PBRC]", 1, + original->PxRcConfig[PCH_PBRC], + params->PxRcConfig[PCH_PBRC]); + soc_display_upd_value("PxRcConfig[PCRC]", 1, + original->PxRcConfig[PCH_PCRC], + params->PxRcConfig[PCH_PCRC]); + soc_display_upd_value("PxRcConfig[PDRC]", 1, + original->PxRcConfig[PCH_PDRC], + params->PxRcConfig[PCH_PDRC]); + soc_display_upd_value("PxRcConfig[PERC]", 1, + original->PxRcConfig[PCH_PERC], + params->PxRcConfig[PCH_PERC]); + soc_display_upd_value("PxRcConfig[PFRC]", 1, + original->PxRcConfig[PCH_PFRC], + params->PxRcConfig[PCH_PFRC]); + soc_display_upd_value("PxRcConfig[PGRC]", 1, + original->PxRcConfig[PCH_PGRC], + params->PxRcConfig[PCH_PGRC]); + soc_display_upd_value("PxRcConfig[PHRC]", 1, + original->PxRcConfig[PCH_PHRC], + params->PxRcConfig[PCH_PHRC]); + soc_display_upd_value("GpioIrqRoute", 1, + original->GpioIrqRoute, + params->GpioIrqRoute); + soc_display_upd_value("SciIrqSelect", 1, + original->SciIrqSelect, + params->SciIrqSelect); + soc_display_upd_value("TcoIrqSelect", 1, + original->TcoIrqSelect, + params->TcoIrqSelect); + soc_display_upd_value("TcoIrqEnable", 1, + original->TcoIrqEnable, + params->TcoIrqEnable); } static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index dd5306e078..b54869c051 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -238,6 +238,13 @@ struct soc_intel_skylake_config { u32 GraphicsConfigPtr; u8 Device4Enable; u8 RtcLock; + /* GPIO IRQ Route The valid values is 14 or 15*/ + u8 GpioIrqSelect; + /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ + u8 SciIrqSelect; + /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/ + u8 TcoIrqSelect; + u8 TcoIrqEnable; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/include/soc/interrupt.h b/src/soc/intel/skylake/include/soc/interrupt.h new file mode 100644 index 0000000000..9fba82964a --- /dev/null +++ b/src/soc/intel/skylake/include/soc/interrupt.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _INTERRUPT_H_ +#define _INTERRUPT_H_ + +/* Number of all PCH devices */ +#define PCH_MAX_DEV_INT_CONFIG 64 + +/* Number of PxRC register in ITSS */ +#define PCH_PARC 0 +#define PCH_PBRC 1 +#define PCH_PCRC 2 +#define PCH_PDRC 3 +#define PCH_PERC 4 +#define PCH_PFRC 5 +#define PCH_PGRC 6 +#define PCH_PHRC 7 +#define PCH_MAX_IRQ_CONFIG 8 + +#define DEVICE_INT_CONFIG(dev, func, line, irqno) {\ + .Device = dev, \ + .Function = func, \ + .IntX = line, \ + .Irq = irqno } + +#define no_int 0 +#define int_A 1 +#define int_B 2 +#define int_C 3 +#define int_D 4 + +#endif /* _INTERRUPT_H_ */ diff --git a/src/soc/intel/skylake/include/soc/irq.h b/src/soc/intel/skylake/include/soc/irq.h index 430a13c38b..fda81423a9 100644 --- a/src/soc/intel/skylake/include/soc/irq.h +++ b/src/soc/intel/skylake/include/soc/irq.h @@ -19,6 +19,26 @@ #define GPIO_IRQ14 14 #define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define SCI_IRQ9 9 +#define SCI_IRQ10 10 +#define SCI_IRQ11 11 +#define SCI_IRQ20 20 +#define SCI_IRQ21 21 +#define SCI_IRQ22 22 +#define SCI_IRQ23 23 + +#define TCO_IRQ9 9 +#define TCO_IRQ10 10 +#define TCO_IRQ11 11 +#define TCO_IRQ20 20 +#define TCO_IRQ21 21 +#define TCO_IRQ22 22 +#define TCO_IRQ23 23 + #define LPSS_I2C0_IRQ 16 #define LPSS_I2C1_IRQ 17 #define LPSS_I2C2_IRQ 18 @@ -32,4 +52,52 @@ #define LPSS_UART2_IRQ 32 #define SDIO_IRQ 22 +#define cAVS_INTA_IRQ 16 +#define SMBUS_INTA_IRQ 16 +#define SMBUS_INTB_IRQ 17 +#define GbE_INTA_IRQ 16 +#define GbE_INTC_IRQ 18 +#define TRACE_HUB_INTA_IRQ 16 +#define TRACE_HUB_INTD_IRQ 19 + +#define eMMC_IRQ 21 +#define SD_IRQ 23 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define IDER_IRQ 18 +#define KT_IRQ 19 +#define HECI_3_IRQ 16 + +#define XHCI_IRQ 16 +#define OTG_IRQ 17 +#define THRMAL_IRQ 18 +#define CIO_INTA_IRQ 16 +#define CIO_INTD_IRQ 19 +#define ISH_IRQ 20 + +#define PEG_RP_INTA_IRQ 16 +#define PEG_RP_INTB_IRQ 17 +#define PEG_RP_INTC_IRQ 18 +#define PEG_RP_INTD_IRQ 19 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define SKYCAM_IRQ 16 +#define GMM_IRQ 16 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 240bd4a4e1..62c9820376 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -48,10 +48,14 @@ #define SA_DEV_IGD _SA_DEV(IGD) /* PCH Devices */ +#define PCH_DEV_SLOT_ISH 0x13 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) + #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) #define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CIO _PCH_DEVFN(XHCI, 3) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) #define PCH_DEV_THERMAL _PCH_DEV(XHCI, 2) @@ -97,6 +101,8 @@ #define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) #define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) #define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) #define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) #define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) #define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) @@ -104,10 +110,19 @@ #define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_SLOT_PCIE_1 0x1d +#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) +#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) + #define PCH_DEV_SLOT_STORAGE 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(STORAGE, 0) #define PCH_DEVFN_UART1 _PCH_DEVFN(STORAGE, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(STORAGE, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(STORAGE, 3) #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 4) +#define PCH_DEVFN_SDIO _PCH_DEVFN(STORAGE, 5) #define PCH_DEVFN_SDCARD _PCH_DEVFN(STORAGE, 6) #define PCH_DEV_UART0 _PCH_DEV(STORAGE, 0) #define PCH_DEV_UART1 _PCH_DEV(STORAGE, 1) @@ -121,6 +136,7 @@ #define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_HDA _PCH_DEV(LPC, 3) |