diff options
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index c362e6c0a9..7a0b8863d7 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -47,6 +47,9 @@ chip soc/intel/apollolake # 0:HS400(Default), 1:HS200, 2:DDR50 register "emmc_host_max_speed" = "2" + # Enable Vtd feature + register "enable_vtd" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index dfdfd551b4..989ab45699 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -46,6 +46,9 @@ chip soc/intel/apollolake # 0:HS400(Default), 1:HS200, 2:DDR50 register "emmc_host_max_speed" = "2" + # Enable Vtd feature + register "enable_vtd" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |