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-rw-r--r--src/cpu/amd/model_gx2/cpubug.c13
-rw-r--r--src/cpu/amd/model_gx2/cpureginit.c5
-rw-r--r--src/cpu/amd/model_gx2/vsmsetup.c16
-rw-r--r--src/northbridge/amd/gx2/chipsetinit.c4
-rw-r--r--src/northbridge/amd/gx2/northbridge.c9
-rw-r--r--src/northbridge/amd/gx2/northbridgeinit.c44
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_setup.c69
7 files changed, 116 insertions, 44 deletions
diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c
index 9b008e627c..3c51208938 100644
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/model_gx2/cpubug.c
@@ -229,7 +229,9 @@ CPUbugIAENG2900 ENDP
#endif
}
-void bug118253(void){
+void bug118253(void)
+{
+ /* GLPCI PIO Post Control shouldn't be enabled */
msr_t msr;
msr = rdmsr(GLPCI_SPARE);
@@ -289,14 +291,13 @@ void bug118339(void)
msr.lo = 0x80004000;
wrmsr(msrnum, msr);
- /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
- /* As per Todd Roberts in PBz1094 and PBz1095 */
- /* Moved from CPUREG to CPUBUG per Tom Sylla */
+ /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
+ /* As per Todd Roberts in PBz1094 and PBz1095 */
+ /* Moved from CPUREG to CPUBUG per Tom Sylla */
msrnum = 0x04C000042; /* GLCP SETMCTL Register */;
msr = rdmsr(msrnum);
- msr.hi |= 8; /* Bit 35 = MCP_IN */
+ msr.hi |= 8; /* Bit 35 = MCP_IN */
wrmsr(msrnum, msr);
-
}
diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index e50079955e..51fbe2ae87 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -169,13 +169,14 @@ cpuRegInit (void){
/* */
/* FooGlue Setup*/
/* */
+#if 0
/* Enable CIS mode B in FooGlue*/
msrnum = MSR_FG + 0x10;
msr = rdmsr(msrnum);
msr.lo &= ~3;
msr.lo |= 2; /* ModeB*/
wrmsr(msrnum, msr);
-
+#endif
/* */
/* Disable DOT PLL. Graphics init will enable it if needed.*/
@@ -209,7 +210,7 @@ cpuRegInit (void){
/* I hate to put this check here but it doesn't really work in cpubug.asm*/
msrnum = MSR_GLCP+0x17;
msr = rdmsr(msrnum);
- if (msr.lo < CPU_REV_2_1){
+ if (msr.lo >= CPU_REV_2_1){
msrnum = CPU_PF_BTB_CONF;
msr = rdmsr(msrnum);
msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c
index 593c7f716b..b462fcd8fd 100644
--- a/src/cpu/amd/model_gx2/vsmsetup.c
+++ b/src/cpu/amd/model_gx2/vsmsetup.c
@@ -195,8 +195,8 @@ static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
/* Dump zeros in the other segregs */
" mov %ax, %es \n"
/* FixMe: Big real mode for gs, fs? */
- //" mov %ax, %fs \n"
- //" mov %ax, %gs \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
" mov $0x40, %ax \n"
" mov %ax, %ds \n"
//" mov %cx, %ax \n"
@@ -277,8 +277,8 @@ void do_vsmbios(void)
memcpy((void *) 0x60000, buf, size);
- for (i = 0; i < 0x800000; i++)
- outb(0xaa, 0x80);
+ //for (i = 0; i < 0x800000; i++)
+ // outb(0xaa, 0x80);
/* ecx gets smm, edx gets sysm */
printk_err("Call real_mode_switch_call_vsm\n");
@@ -568,8 +568,6 @@ void setup_realmode_idt(void)
idts[1].cs = 0;
idts[1].offset = 16384;
memcpy(16384, &debughandle, &end_debughandle - &debughandle);
-
-
}
@@ -745,6 +743,12 @@ int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
case 0x5f0f:
*eax=0x860f;
break;
+ case 0xBEA7:
+ *eax=33;
+ break;
+ case 0xBEA4:
+ *eax=333;
+ break;
}
return res;
}
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c
index 3d1f6ce4c1..2a1688a014 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/northbridge/amd/gx2/chipsetinit.c
@@ -211,6 +211,7 @@ chipsetinit (void){
outb( P80_CHIPSET_INIT, 0x80);
ChipsetGeodeLinkInit();
+#if 0
/* we hope NEVER to be in linuxbios when S3 resumes
if (! IsS3Resume()) */
{
@@ -227,6 +228,7 @@ chipsetinit (void){
pmChipsetInit();
}
+#endif
/* for later ... if 5536 set_usb_20(); */
@@ -250,7 +252,7 @@ chipsetinit (void){
msr.lo &= ~0x100;
wrmsr(msrnum, msr);
-/* Enable Post Primary IDE.*/
+ /* Enable Post Primary IDE.*/
msrnum = GLPCI_SB_CTRL;
msr = rdmsr(msrnum);
msr.lo |= GLPCI_CRTL_PPIDE_SET;
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index af3fe7873f..7c3cb52623 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -102,10 +102,10 @@ struct msr_defaults {
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
/* we will not set 0x180f, the DMM,yet */
- {0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
- {0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
- {0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
- {0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
+ //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
+ //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
+ //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
+ //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
/* now for GLPCI routing */
/* GLIU0 */
P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
@@ -424,6 +424,7 @@ static void enable_dev(struct device *dev)
extern void cpubug(void);
printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_gx2(), so we force the issue here */
+ northbridgeinit();
cpubug();
chipsetinit();
setup_gx2();
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 5c0a1985b8..6f638c244e 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -22,14 +22,14 @@ struct gliutable {
};
struct gliutable gliu0table[] = {
- {.desc_name=MSR_GLIU0_BASE1,.desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
- {.desc_name=MSR_GLIU0_BASE2,.desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
- {.desc_name=MSR_GLIU0_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
- {.desc_name=MSR_GLIU0_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
- {.desc_name=MSR_GLIU0_DMM,.desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
- {.desc_name=MSR_GLIU0_SMM,.desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
+ {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
+ {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
+ {.desc_name=MSR_GLIU0_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
+ {.desc_name=MSR_GLIU0_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
+ {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
+ {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
- {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+ {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
@@ -45,17 +45,12 @@ struct gliutable gliu1table[] = {
{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
-
-
-
-
-
-
struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
- struct msrinit {
+struct msrinit {
unsigned long msrnum;
- msr_t msr;};
+ msr_t msr;
+};
struct msrinit ClockGatingDefault [] = {
{GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
@@ -100,11 +95,11 @@ struct msrinit GeodeLinkPriorityTable [] = {
{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/
{VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/
{GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/
- {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, /* GLPCI Priority + PID*/
+ {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, /* GLPCI Priority + PID*/
{GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID*/
{VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID*/
{AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID*/
- {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/
+ {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/
};
/* do we have dmi or not? assume yes */
@@ -124,7 +119,8 @@ writeglmsr(struct gliutable *gl){
}
static void
-ShadowInit(struct gliutable *gl) {
+ShadowInit(struct gliutable *gl)
+{
msr_t msr;
msr = rdmsr(gl->desc_name);
@@ -141,9 +137,8 @@ ShadowInit(struct gliutable *gl) {
*/
extern int sizeram(void);
static void
-SysmemInit(struct gliutable *gl) {
-
-
+SysmemInit(struct gliutable *gl)
+{
msr_t msr;
int sizembytes, sizebytes;
@@ -515,6 +510,7 @@ performance:
printk_debug("%s: MSR 0x%x will be set to 0x%x:0x%x\n", __FUNCTION__,
gating->msrnum, msr.hi, msr.lo);
wrmsr(gating->msrnum, msr);
+ gating +=1;
}
}
@@ -534,6 +530,7 @@ GeodeLinkPriority(void){
printk_debug("%s: MSR 0x%x will be set to 0x%x:0x%x\n", __FUNCTION__,
prio->msrnum, msr.hi, msr.lo);
wrmsr(prio->msrnum, msr);
+ prio +=1;
}
}
@@ -550,10 +547,11 @@ GeodeLinkPriority(void){
/* ***************************************************************************/
void
-northbridgeinit(void){
+northbridgeinit(void)
+{
int i;
printk_debug("Enter %s\n", __FUNCTION__);
-// post(POST_NORTHB_INIT);
+
for(i = 0; gliutables[i]; i++)
GLIUInit(gliutables[i]);
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index e6b36435b2..e0f2b146af 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -37,6 +37,20 @@ static void cs5535_setup_idsel(void)
outl(0x1 << (CS5535_DEV_NUM + 10), 0);
}
+static void cs5535_usb_swapsif(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(0x51600005);
+ //USB Serial short detect bit.
+ if (msr.hi & 0x10) {
+ /* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
+ * SERSHRT error bit */
+ msr.hi &= 0xFFFFFFFB;
+ wrmsr(0x51600005, msr);
+ }
+}
+
static int cs5535_setup_iobase(void)
{
msr_t msr;
@@ -49,10 +63,36 @@ static int cs5535_setup_iobase(void)
__builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
/* setup LBAR for ACPI */
__builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
- /* setup LBAR for MFGPT */
+ /* setup LBAR for PM Support */
__builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
}
+static void cs5535_setup_power_bottun(void)
+{
+ /* not implemented yet */
+#if 0
+ pwrBtn_setup:
+ ;
+ ; Power Button Setup
+ ;
+ ;mov eax, 0C0020000h ; 4 seconds + lock
+ mov eax, 040020000h ; 4 seconds no lock
+ mov dx, PMLogic_BASE + 40h
+ out dx, eax
+
+ ; setup GPIO24, it is the external signal for 5535 vsb_work_aux
+ ; which controls all voltage rails except Vstandby & Vmem.
+ ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
+ ; If GPIO24 is not enabled then soft-off will not work.
+ mov dx, GPIOH_OUT_AUX1_SELECT
+ mov eax, GPIOH_24_SET
+ out dx, eax
+ mov dx, GPIOH_OUTPUT_ENABLE
+ out dx, eax
+
+#endif
+}
+
static void cs5535_setup_gpio(void)
{
uint32_t val;
@@ -75,6 +115,29 @@ static void cs5535_setup_gpio(void)
//outl(val, 0x6100 + 0x34);
}
+static void cs5535_disable_internal_uart(void)
+{
+ /* not implemented yet */
+#if 0
+ ; The UARTs default to enabled.
+ ; Disable and reset them and configure them later. (SIO init)
+ mov ecx, MDD_UART1_CONF
+ RDMSR
+ mov eax, 1h ; reset
+ WRMSR
+ mov eax, 0h ; disabled
+ WRMSR
+
+ mov ecx, MDD_UART2_CONF
+ RDMSR
+ mov eax, 1h ; reset
+ WRMSR
+ mov eax, 0h ; disabled
+ WRMSR
+
+#endif
+}
+
static void cs5535_setup_cis_mode(void)
{
msr_t msr;
@@ -84,7 +147,8 @@ static void cs5535_setup_cis_mode(void)
msr.lo &= ~0x18;
msr.lo |= 0x10;
__builtin_wrmsr(0x51000010, msr.lo, msr.hi);
- __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
+ //Only do this if we are building for 5535
+ //__builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
}
static void dummy(void)
@@ -106,6 +170,7 @@ static int cs5535_early_setup(void)
print_debug("Setup idsel\r\n");
cs5535_setup_idsel();
print_debug("Setup iobase\r\n");
+ cs5535_usb_swapsif();
cs5535_setup_iobase();
print_debug("Setup gpio\r\n");
cs5535_setup_gpio();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 20:45:31 +0000