diff options
| -rw-r--r-- | src/include/cpu/x86/cache.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 14538592e9..858637cf2b 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -23,6 +23,17 @@ /* the memory clobber prevents the GCC from reordering the read/write order of CR0 */ + */ + +#if defined(__GNUC__) + +/* +Need this because ROMCC fails here with: + +cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: +0x1559920 asm Internal compiler error: lhs 1 regcm == 0 +*/ + static inline unsigned long read_cr0(void) { unsigned long cr0; @@ -35,6 +46,23 @@ static inline void write_cr0(unsigned long cr0) asm volatile ("movl %0, %%cr0" : : "r" (cr0) : "memory"); } +#else + +static inline unsigned long read_cr0(void) +{ + unsigned long cr0; + asm volatile ("movl %%cr0, %0" : "=r" (cr0)); + return cr0; +} + +static inline void write_cr0(unsigned long cr0) +{ + asm volatile ("movl %0, %%cr0" : : "r" (cr0)); +} + +#endif + + static inline void invd(void) { asm volatile("invd" ::: "memory"); |