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-rw-r--r--Documentation/Intel/NativeRaminit/Sandybridge.md25
1 files changed, 18 insertions, 7 deletions
diff --git a/Documentation/Intel/NativeRaminit/Sandybridge.md b/Documentation/Intel/NativeRaminit/Sandybridge.md
index 8203106c07..5c83a0dad2 100644
--- a/Documentation/Intel/NativeRaminit/Sandybridge.md
+++ b/Documentation/Intel/NativeRaminit/Sandybridge.md
@@ -18,16 +18,27 @@ The memory initialization code has to take care of lots of duties:
* Error handling
## Definitions
+```eval_rst
++---------+-------------------------------------------------------------------+------------+--------------+
| Symbol | Description | Units | Valid region |
-|---------|-------------------------------------------------------------------|------------|--------------|
-| SCK | DRAM system clock cycle time | s | - |
-| tCK | DRAM system clock cycle time | 1/256th ns | - |
-| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
++=========+===================================================================+============+==============+
+| SCK | DRAM system clock cycle time | s | |
++---------+-------------------------------------------------------------------+------------+--------------+
+| tCK | DRAM system clock cycle time | 1/256th ns | |
++---------+-------------------------------------------------------------------+------------+--------------+
+| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
++---------+-------------------------------------------------------------------+------------+--------------+
| timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |
-| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
++---------+-------------------------------------------------------------------+------------+--------------+
+| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
++---------+-------------------------------------------------------------------+------------+--------------+
| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
-| MULT | DRAM PLL multiplier | - | [3-12] |
-| XMP | Extreme Memory Profiles | - | - |
++---------+-------------------------------------------------------------------+------------+--------------+
+| MULT | DRAM PLL multiplier | | [3-12] |
++---------+-------------------------------------------------------------------+------------+--------------+
+| XMP | Extreme Memory Profiles | | |
++---------+-------------------------------------------------------------------+------------+--------------+
+```
## (Inoffical) register documentation
- [Sandy Bride - Register documentation](SandyBridge_registers.md)