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-rw-r--r--Documentation/mainboard/sifive/hifive-unleashed.md1
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diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
index 495dade212..4dbbf0e073 100644
--- a/Documentation/mainboard/sifive/hifive-unleashed.md
+++ b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -17,7 +17,6 @@ The following things are still missing from this coreboot port:
- Provide serial number to payload (e.g. in device tree)
- Implement instruction emulation
- Support for booting Linux on RISC-V
-- Add support to run OpenSBI payload in m-mode
- SMP support in trap handler
## Configuration