summaryrefslogtreecommitdiff
path: root/Documentation/soc/intel/fsp/index.md
diff options
context:
space:
mode:
Diffstat (limited to 'Documentation/soc/intel/fsp/index.md')
-rw-r--r--Documentation/soc/intel/fsp/index.md6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
index aac7b35a50..769b98b4fc 100644
--- a/Documentation/soc/intel/fsp/index.md
+++ b/Documentation/soc/intel/fsp/index.md
@@ -34,6 +34,11 @@ those are fixed. If possible a workaround is described here as well.
* Workaround: none
* Issue on public tracker: [Issue 22]
+* MRC forces memory re-training on cold boot on boards with Intel SPS
+ * Releases 3.7.1, 3.7.6
+ * Workaround: Flash Intel ME instead of SPS
+ * Issue on public tracker: [Issue 41]
+
### BraswellFsp
* Internal UART can't be disabled using PcdEnableHsuart*
* Release MR2
@@ -66,4 +71,5 @@ those are fixed. If possible a workaround is described here as well.
[Issue 15]: https://github.com/IntelFsp/FSP/issues/15
[Issue 22]: https://github.com/IntelFsp/FSP/issues/22
[Issue 35]: https://github.com/IntelFsp/FSP/issues/35
+[Issue 41]: https://github.com/IntelFsp/FSP/issues/41