2 files changed, 16 insertions, 2 deletions
diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md
index 9a5de34f09..ea6a5cd47e 100644
--- a/Documentation/arch/riscv/index.md
+++ b/Documentation/arch/riscv/index.md
@@ -23,8 +23,20 @@ On entry to a stage or payload (including SELF payloads),
 ## Additional payload handoff requirements
 The location of cbmem should be placed in a node in the FDT.
 
+## OpenSBI
+In case the payload doesn't install it's own SBI, like the [RISCV-PK] does,
+[OpenSBI] can be used instead.
+It's loaded into RAM after coreboot has finished loading the payload.
+coreboot then will jump to OpenSBI providing a pointer to the real payload,
+which OpenSBI will jump to once the SBI is installed.
+
+Besides providing SBI it also sets protected memory regions and provides
+a platform independent console.
+
+The OpenSBI code is always run in M mode.
+
 ## Trap delegation
-Traps are delegated in the ramstage.
+Traps are delegated to the payload.
 
 ## SMP within a stage
 At the beginning of each stage, all harts save 0 are spinning in a loop on
@@ -44,3 +56,6 @@ The hart blocks until fn is non-null, and then calls it.  If fn returns, we
 will panic if possible, but behavior is largely undefined.
 
 Only hart 0 runs through most of the code in each stage.
+
+[RISCV-PK]: https://github.com/riscv/riscv-pk
+[OpenSBI]: https://github.com/riscv/opensbi
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
index 495dade212..4dbbf0e073 100644
--- a/Documentation/mainboard/sifive/hifive-unleashed.md
+++ b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -17,7 +17,6 @@ The following things are still missing from this coreboot port:
 - Provide serial number to payload (e.g. in device tree)
 - Implement instruction emulation
 - Support for booting Linux on RISC-V
-- Add support to run OpenSBI payload in m-mode
 - SMP support in trap handler
 
 ## Configuration