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-rw-r--r--Documentation/Intel/Board/Galileo_checklist.html2
-rw-r--r--Documentation/Intel/SoC/soc.html2
2 files changed, 0 insertions, 4 deletions
diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html
index 3fc04b18ce..397f570b0e 100644
--- a/Documentation/Intel/Board/Galileo_checklist.html
+++ b/Documentation/Intel/Board/Galileo_checklist.html
@@ -79,8 +79,6 @@
<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr>
<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr>
<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr>
-<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr>
-<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr>
<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr>
<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr>
<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 29b819ec82..fff536b9b1 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -234,8 +234,6 @@ Use the following steps to locate the FSP binary:
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
</li>
<li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
- specifically building
- <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
</li>
</ol>
</li>