diff options
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/flash_tutorial/ext_power.md | 28 | ||||
| -rw-r--r-- | Documentation/flash_tutorial/ext_standalone.md | 23 | ||||
| -rw-r--r-- | Documentation/flash_tutorial/flash_ic_diode.svg | 61 | ||||
| -rw-r--r-- | Documentation/flash_tutorial/flash_ic_no_diode.svg | 55 | ||||
| -rw-r--r-- | Documentation/flash_tutorial/index.md | 105 | ||||
| -rw-r--r-- | Documentation/flash_tutorial/int_flashrom.md | 19 | ||||
| -rw-r--r-- | Documentation/flash_tutorial/no_ext_power.md | 22 | ||||
| -rw-r--r-- | Documentation/index.md | 1 | ||||
| -rw-r--r-- | Documentation/mainboard/index.md | 14 | ||||
| -rw-r--r-- | Documentation/mainboard/lenovo/flashlayout_xx20.svg | 52 | ||||
| -rw-r--r-- | Documentation/mainboard/lenovo/flashlayout_xx30.svg | 61 | ||||
| -rw-r--r-- | Documentation/mainboard/lenovo/t420.md | 16 | ||||
| -rw-r--r-- | Documentation/mainboard/lenovo/t430.md | 15 | ||||
| -rw-r--r-- | Documentation/mainboard/lenovo/t4xx_series.md | 20 | ||||
| -rw-r--r-- | Documentation/mainboard/lenovo/xx20_series.md | 48 | ||||
| -rw-r--r-- | Documentation/mainboard/lenovo/xx30_series.md | 76 |
16 files changed, 616 insertions, 0 deletions
diff --git a/Documentation/flash_tutorial/ext_power.md b/Documentation/flash_tutorial/ext_power.md new file mode 100644 index 0000000000..542ccfd934 --- /dev/null +++ b/Documentation/flash_tutorial/ext_power.md @@ -0,0 +1,28 @@ +# Flashing firmware externally supplying direct power + +**WARNING:** Never use a high current rated power supply, like PC ATX power + supply. It'll literally melt your PCB traces on short circuit. + +On some mainboards the flash IC Vcc pin is connected to a diode, which prevents +powering the rest of the board. + +![][flash_ic_diode] + +Please have a look at the mainboard specific documentation for details. + +On those boards it's safe to use a programmer and supply power externally. + +**WARNING:** Verify that you apply the correct voltage! + +## USB programmer +USB programmers are usually current limited by the host USB hub. On USB 2.0 +ports the limit is 500mA, which is sufficient to power the flash. Those are +the best choice as they are stateless and have a fast power on reset cycle. + +## Single board computers (like BeagleBone Black / RPi) +Be careful when connecting a flash chip, especially when using a Pomona +test-clip. A short circuit or overcurrent (250mA) causes a brown-out reset, +resulting in a reboot of the running operating system (and possible loss of +remote shell). + +[flash_ic_diode]: flash_ic_diode.svg diff --git a/Documentation/flash_tutorial/ext_standalone.md b/Documentation/flash_tutorial/ext_standalone.md new file mode 100644 index 0000000000..3a676ce47c --- /dev/null +++ b/Documentation/flash_tutorial/ext_standalone.md @@ -0,0 +1,23 @@ +# Flashing firmware standalone + +If none of the other methods work, there are three possibilities: + +## Desolder +You must remove or desolder the flash IC before you can flash it. +It's recommended to solder a socket in place of the flash IC. + +When flashing the IC, always connect all input pins. +If in doubt, pull /WP, /HOLD, /RESET and alike up towards Vcc. + +## SPI flash emulator +If you are a developer, you might want to use an [EM100Pro] instead, which sets +the onboard flash on hold, and allows to run custom firmware. +It provides a very fast development cycle without actually writing to flash. + +## SPI flash overwrite +It is possible to set the onboard flash on hold and use another flash chip. +Connect all lines one-to-one, except /HOLD. Pull /HOLD of the soldered flash IC +low, and /HOLD of your replacement flash IC high. + + +[EM100Pro]: https://www.dediprog.com/product/EM100Pro diff --git a/Documentation/flash_tutorial/flash_ic_diode.svg b/Documentation/flash_tutorial/flash_ic_diode.svg new file mode 100644 index 0000000000..22cd87277f --- /dev/null +++ b/Documentation/flash_tutorial/flash_ic_diode.svg @@ -0,0 +1,61 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="4cm" height="3cm" viewBox="311 435 68 45" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <g> + <rect style="fill: #ffffff" x="322.125" y="451.034" width="37.75" height="26.6444"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="322.125" y="451.034" width="37.75" height="26.6444"/> + <text font-size="4.51549" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="341" y="465.734"> + <tspan x="341" y="465.734"></tspan> + </text> + </g> + <line style="fill: none; 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You need to buy a flash programmer, that +exposes the same interface as your flash IC (likely SPI). + +Please also have a look at the mainboard-specific documentation for details. + +After exposing the firmware flash IC, read the schematics and use one of the +possible methods: + +* [Flashing firmware standalone](ext_standalone.md) +* [Flashing firmware externally supplying direct power](ext_power.md) +* [Flashing firmware externally without supplying direct power](no_ext_power.md) + +**WARNING:** Using the wrong method or accidentally using the wrong pinout might + permanently damage your hardware! + +## Using a layout file +On platforms where the flash IC is shared with other components you might want +to write only a part of the flash IC. On Intel for example there are IFD, ME and +GBE which don't need to be updated to install coreboot. +To make [flashrom] only write the *bios* region, leaving Intel ME and Intel IFD +untouched, you can use a layout file, which can be created using ifdtool + +```bash +ifdtool -f rom.layout coreboot.rom +``` + +and looks similar to: + +``` +00000000:00000fff fd +00500000:00bfffff bios +00003000:004fffff me +00001000:00002fff gbe +``` + +By specifying *-l* and *-i* [flashrom] writes a single region: +```bash +flashrom -l rom.layout -i bios -w coreboot.rom -p <programmer> +``` + +## Using an IFD to determine the layout +flashrom version 1.0 supports reading the layout from the IFD (first 4KiB of +the ROM). You don't need to manually specify a layout it, but it only works +under the following conditions: + +* Only available on Intel ICH7+ +* There's only one flash IC when flashing externally + +```bash +flashrom --ifd -i bios -w coreboot.rom -p <programmer> +``` + +**TODO** explain FMAP regions, normal/fallback mechanism, flash lock mechanisms + +[flashrom]: https://www.flashrom.org/Flashrom diff --git a/Documentation/flash_tutorial/int_flashrom.md b/Documentation/flash_tutorial/int_flashrom.md new file mode 100644 index 0000000000..28b534b003 --- /dev/null +++ b/Documentation/flash_tutorial/int_flashrom.md @@ -0,0 +1,19 @@ +# Flashing firmware internally + +**WARNING:** If you flash a broken firmware and have no recovery mechanism, you + must use the **external method** to flash a working firmware again. + +## Using flashrom +This method does only work on Linux, if it isn't locked down. +You may also need to boot with 'iomem=relaxed' in the kernel command +line if CONFIG_IO_STRICT_DEVMEM is set. + + +For more details please also check [flashrom's wiki]. +Use the programmer *internal* to flash *coreboot.rom* internally: + +```bash +flashrom -p internal -w coreboot.rom +``` + +[flashrom's wiki]: https://www.flashrom.org/Flashrom diff --git a/Documentation/flash_tutorial/no_ext_power.md b/Documentation/flash_tutorial/no_ext_power.md new file mode 100644 index 0000000000..b97ba4cc7a --- /dev/null +++ b/Documentation/flash_tutorial/no_ext_power.md @@ -0,0 +1,22 @@ +# Flashing firmware externally supplying no power + +On some mainboards the flash IC's Vcc pin is connected to the internal +power-rail, powering the entire board if the flash IC is powered externally. +Likely it powers other chips which access the flash IC, preventing the external +programmer from reading/writing the chip. It also violates the components' +power sequence, bringing the ICs into an undefined state. + +![][flash_ic_no_diode] + +Please have a look at the mainboard specific documentation for details. + +On those boards it's recommended to use a programmer without supplying power +externally. + +The key to read and write the flash IC is to put the machine into *S3* sleep- +state or *S5* sleep-state *maybe* with Wake-On-LAN enabled. +Another option that sometimes works is to keep the device in reset. This method requires +knowledge of the board schematics and might require hardware modifications. +Use a multimeter to make sure the flash IC is powered in those sleep states. + +[flash_ic_no_diode]: flash_ic_no_diode.svg diff --git a/Documentation/index.md b/Documentation/index.md index b20eedc10f..e69f2ea7d5 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -23,3 +23,4 @@ Contents: * [Vendorcode-specific documentation](vendorcode/index.md) * [Utilities](util.md) * [Release notes for past releases](releases/index.md) +* [Flashing firmware tutorial](flash_tutorial/index.md) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 45eb217e4d..c346a3b8f0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -26,6 +26,20 @@ This section contains documentation about coreboot on specific mainboards. - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) +## Lenovo + +- [T4xx common](lenovo/t4xx_series.md) + +### Sandy Bridge series + +- [T420](lenovo/t420.md) +- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md) + +### Ivy Bridge series + +- [T430](lenovo/t430.md) +- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) + ## SiFive - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) diff --git a/Documentation/mainboard/lenovo/flashlayout_xx20.svg b/Documentation/mainboard/lenovo/flashlayout_xx20.svg new file mode 100644 index 0000000000..8884ac37ad --- /dev/null +++ b/Documentation/mainboard/lenovo/flashlayout_xx20.svg @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="10cm" height="8cm" viewBox="265 -156 186 159" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 380.877 -151.013 C 401.876,-151.013 379.377,-73.513 400.627,-72.513"/> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.377 -0.763268 C 395.238,-0.763268 387.016,-72.763 400.877,-72.763"/> + <text font-size="10.1598" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="406.127" y="-68.513"> + <tspan x="406.127" y="-68.513">Flash #0</tspan> + </text> +</svg> diff --git a/Documentation/mainboard/lenovo/flashlayout_xx30.svg b/Documentation/mainboard/lenovo/flashlayout_xx30.svg new file mode 100644 index 0000000000..5cc4e4fbaf --- /dev/null +++ b/Documentation/mainboard/lenovo/flashlayout_xx30.svg @@ -0,0 +1,61 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="10cm" height="11cm" viewBox="265 -156 187 213" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 2; stroke: #000000" x="308" y="-121.59" width="49.1438" height="30.4667"/> + <text font-size="6.77333" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="332.572" y="-104.29"> + <tspan x="332.572" y="-104.29">GBE</tspan> + </text> + </g> + <text font-size="6.77333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="265.968" y="-149.208"> + <tspan x="265.968" y="-149.208">0x000000</tspan> + </text> + <text font-size="6.77333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="266.362" y="-120.102"> + <tspan x="266.362" y="-120.102">0x001000</tspan> + </text> + <text font-size="6.77333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="266.162" y="-88.8972"> + <tspan x="266.162" y="-88.8972">0x003000</tspan> + </text> + <text font-size="6.77333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="266.144" y="-29.6656"> + <tspan x="266.144" y="-29.6656">0x500000</tspan> + </text> + <text font-size="6.77333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="266.326" y="1.87412"> + <tspan x="266.326" y="1.87412">0x800000</tspan> + </text> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 380.877 -151.013 C 401.876,-151.013 379.377,-73.513 400.627,-72.513"/> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.377 -0.763268 C 395.238,-0.763268 387.016,-72.763 400.877,-72.763"/> + <text font-size="10.1598" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="406.127" y="-68.513"> + <tspan x="406.127" y="-68.513">Flash #0</tspan> + </text> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.223 -0.537117 C 402.222,-0.537117 379.285,28.8102 399.872,27.8376"/> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 382.176 54.9128 C 396.037,54.9128 385.445,27.9997 399.548,27.8376"/> + <text font-size="10.1598" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="407.157" y="30.2529"> + <tspan x="407.157" y="30.2529">Flash #1</tspan> + </text> + <text font-size="6.77333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="266.591" y="54.9733"> + <tspan x="266.591" y="54.9733">0xc00000</tspan> + </text> + <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke-dasharray: 4; stroke: #000000" x1="305.271" y1="-1.2113" x2="378.831" y2="-1.17038"/> +</svg> diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md new file mode 100644 index 0000000000..ff7a0a9238 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420.md @@ -0,0 +1,16 @@ +# Lenovo T420 + +## Flashing instructions +You have to disassemble the whole device, as the flash IC is on the bottom +of the mainboard. + +For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and + +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md +[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md new file mode 100644 index 0000000000..787246f4d4 --- /dev/null +++ b/Documentation/mainboard/lenovo/t430.md @@ -0,0 +1,15 @@ +# Lenovo T430 + +## Flashing instructions +You have to disassemble the whole device, as the flash ICs are on the bottom +of the mainboard. + +For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md +[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md diff --git a/Documentation/mainboard/lenovo/t4xx_series.md b/Documentation/mainboard/lenovo/t4xx_series.md new file mode 100644 index 0000000000..23fe0fbe53 --- /dev/null +++ b/Documentation/mainboard/lenovo/t4xx_series.md @@ -0,0 +1,20 @@ +# Lenovo T4xx series disassembly instructions + +A skilled engineer takes around 40 minutes to disassemble, flash and reassemble +the whole device. + +# Steps to access the flash IC: + +* Unplug the main battery +* Remove the harddisk, CDROM, ExpressCard, SIM-card, SDcard, SmartCard, ... +* Open the bottom flap and remove the keyboard screw +* Remove the keyboard +* Remove the screen +* Remove the top enclosure +* Remove the CMOS battery +* Remove the speakers +* Remove WWAN and WIFI card +* Remove the CPU fan +* Unplug the power cable +* Remove the bottom enclosure +* Flip the mainboard and remove the main frame diff --git a/Documentation/mainboard/lenovo/xx20_series.md b/Documentation/mainboard/lenovo/xx20_series.md new file mode 100644 index 0000000000..976a29ba9f --- /dev/null +++ b/Documentation/mainboard/lenovo/xx20_series.md @@ -0,0 +1,48 @@ +# Lenovo Sandy Bridge series + +## Flashing coreboot +```eval_rst ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Socketed flash | no | ++---------------------+--------------------+ +| Size | 8 MiB | ++---------------------+--------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| Write protection | No | ++---------------------+--------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------+ +| Internal flashing | Yes | ++---------------------+--------------------+ +``` + +## Installation instructions +* Update the EC firmware, as there's no support for EC updates in coreboot. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will destroy your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract BLOBs from vendor firmware. + If you want to flash the whole chip, you need BLOBs when building + coreboot. +* The shipped *Flash layout* allocates 3MiB to the BIOS region, which is the space + usable by coreboot. +* ROM chip size should be set to 8MiB. + +```eval_rst +Please also have a look at :doc:`../../flash_tutorial/index`. +``` + +## Flash layout +There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions. +On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS +region. The update is then written into the EC once. + +![][fl] + +[fl]: flashlayout_xx20.svg + diff --git a/Documentation/mainboard/lenovo/xx30_series.md b/Documentation/mainboard/lenovo/xx30_series.md new file mode 100644 index 0000000000..e65a3f2a6f --- /dev/null +++ b/Documentation/mainboard/lenovo/xx30_series.md @@ -0,0 +1,76 @@ +# Lenovo Ivy Bridge series + +## Flashing coreboot +```eval_rst ++---------------------+--------------------------------+ +| Type | Value | ++=====================+================================+ +| Socketed flash | no | ++---------------------+--------------------------------+ +| Size | 8 MiB + 4MiB | ++---------------------+--------------------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------------------+ +| Package | SOIC-8 | ++---------------------+--------------------------------+ +| Write protection | No | ++---------------------+--------------------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------------------+ +| Internal flashing | Yes | ++---------------------+--------------------------------+ +``` + +## Installation instructions +* Update the EC firmware, as there's no support for EC updates in coreboot. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will permanently brick your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract BLOBs from vendor firmware. + If you want to flash the whole chip, you need BLOBs when building + coreboot. +* The *Flash layout* shows that by default 7MiB of space are available for + the use with coreboot. +* In that case you only want to use a part of the BIOS region that must not + exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB. +* ROM chip size should be set to 12MiB. + +```eval_rst +Please also have a look at :doc:`../../flash_tutorial/index`. +``` + +## Splitting the coreboot.rom + +To split the coreboot.rom into two images (one for the 8MiB and one for the +4 MiB flash IC), run the following commands: + +```bash +dd of=top.rom bs=1M if=build/coreboot.rom skip=8 +dd of=bottom.rom bs=1M if=build/coreboot.rom count=8 +``` + +That gives one ROM for each flash IC, where *top.rom* is the upper part of the +flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part +of the flash image, that resides on the 8 MiB flash. + +## Dumping a full ROM + +If you flash externally you need to read both flash chips to get two images +(one for the 8MiB and one for the 4 MiB flash IC), and then run the following +command to concatenate the files: + +```bash +cat bottom.rom top.rom > firmware.rom +``` + +## Flash layout +There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and +BIOS region. These two flash ICs appear as a single 12MiB when flashing +internally. +On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS +region. The update is then written into the EC once. + +![][fl] + +[fl]: flashlayout_xx30.svg + |
