diff options
Diffstat (limited to 'payloads/libpayload/include')
| -rw-r--r-- | payloads/libpayload/include/arm/arch/cache.h | 19 | ||||
| -rw-r--r-- | payloads/libpayload/include/x86/arch/cache.h | 2 |
2 files changed, 3 insertions, 18 deletions
diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h index 5210dfe6a8..470eb55108 100644 --- a/payloads/libpayload/include/arm/arch/cache.h +++ b/payloads/libpayload/include/arm/arch/cache.h @@ -93,18 +93,6 @@ static inline void isb(void) * Low-level TLB maintenance operations */ -/* invalidate entire data TLB */ -static inline void dtlbiall(void) -{ - asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory"); -} - -/* invalidate entire instruction TLB */ -static inline void itlbiall(void) -{ - asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); -} - /* invalidate entire unified TLB */ static inline void tlbiall(void) { @@ -313,8 +301,8 @@ void dcache_mmu_disable(void); /* dcache and MMU enable */ void dcache_mmu_enable(void); -/* icache invalidate all (on current level given by CSSELR) */ -void icache_invalidate_all(void); +/* perform all icache/dcache maintenance needed after loading new code */ +void cache_sync_instructions(void); /* tlb invalidate all */ void tlb_invalidate_all(void); @@ -323,9 +311,6 @@ void tlb_invalidate_all(void); * Generalized setup/init functions */ -/* invalidate all caches on ARM */ -void arm_invalidate_caches(void); - /* mmu initialization (set page table address, set permissions, etc) */ void mmu_init(void); diff --git a/payloads/libpayload/include/x86/arch/cache.h b/payloads/libpayload/include/x86/arch/cache.h index 396048802f..ffefcdbe19 100644 --- a/payloads/libpayload/include/x86/arch/cache.h +++ b/payloads/libpayload/include/x86/arch/cache.h @@ -41,6 +41,6 @@ #define dcache_invalidate_by_mva(addr, len) #define dcache_clean_invalidate_all() #define dcache_clean_invalidate_by_mva(addr, len) -#define icache_invalidate_all() +#define cache_sync_instructions() #endif |