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-rw-r--r--payloads/libpayload/arch/mips/timer.c21
1 files changed, 17 insertions, 4 deletions
diff --git a/payloads/libpayload/arch/mips/timer.c b/payloads/libpayload/arch/mips/timer.c
index 1710a322e2..782959b71a 100644
--- a/payloads/libpayload/arch/mips/timer.c
+++ b/payloads/libpayload/arch/mips/timer.c
@@ -19,6 +19,10 @@
#include <libpayload.h>
#include <arch/cpu.h>
+#include <arch/io.h>
+
+#define PISTACHIO_CLOCK_SWITCH 0xB8144200
+#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
/**
* @ingroup arch
@@ -34,10 +38,19 @@ u32 cpu_khz;
unsigned int get_cpu_speed(void)
{
if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
- cpu_khz = 50000U; /* FPGA board */
- /* else {
- * TODO find CPU frequency on the real SOC
- } */
+ cpu_khz = 50000; /* FPGA board */
+ else {
+ /* If MIPS PLL external bypass bit is set, it means
+ * that the MIPS PLL is already set up to work at a
+ * frequency of 550 MHz; otherwise, the crystal is
+ * used with a frequency of 52 MHz
+ */
+ if (read32(PISTACHIO_CLOCK_SWITCH) &
+ MIPS_EXTERN_PLL_BYPASS_MASK)
+ cpu_khz = 550000;
+ else
+ cpu_khz = 52000;
+ }
return cpu_khz;
}