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-rw-r--r--src/arch/arm64/include/arch/header.ld6
-rw-r--r--src/arch/arm64/include/arch/memlayout.h8
-rw-r--r--src/arch/arm64/include/armv8/arch/exception.h4
3 files changed, 8 insertions, 10 deletions
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index 2ea0a19304..c82cb3f8c7 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -24,11 +24,7 @@ PHDRS
to_load PT_LOAD;
}
-#if ENV_BOOTBLOCK
-TARGET(binary)
-#endif
-
-#if ENV_RMODULE
+#if ENV_BOOTBLOCK || ENV_RMODULE
ENTRY(_start)
#else
ENTRY(stage_entry)
diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h
index ea4a1ba80c..6db67a9dee 100644
--- a/src/arch/arm64/include/arch/memlayout.h
+++ b/src/arch/arm64/include/arch/memlayout.h
@@ -22,13 +22,13 @@
REGION(ttb, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!");
-/* ARM64 stacks need 16-byte alignment. The ramstage will set up its own stacks
- * in BSS, so this is only used for the SRAM stages. */
-#ifdef __PRE_RAM__
+/* ARM64 stacks need 16-byte alignment. */
+#if !(IS_ENABLED(CONFIG_SOC_NVIDIA_TEGRA132) || \
+ IS_ENABLED(CONFIG_SOC_NVIDIA_TEGRA210))
#define STACK(addr, size) \
REGION(stack, addr, size, 16) \
_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc");
-#else
+#else /* Hack around old Tegra stage_entry.S implementation. TODO: remove */
#define STACK(addr, size) REGION(preram_stack, addr, size, 16)
#endif
diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h
index 49ea747700..0ec0eea953 100644
--- a/src/arch/arm64/include/armv8/arch/exception.h
+++ b/src/arch/arm64/include/armv8/arch/exception.h
@@ -33,9 +33,11 @@
#include <arch/transition.h>
/* Initialize the exception handling on the current CPU. */
-void exception_hwinit(void);
void exception_init(void);
+/* Initialize VBAR and SP_EL3. */
+void exception_init_asm(void *exception_stack_end);
+
/*
* Order matters for handling return values. The larger the value the higher
* the precedence.