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-rw-r--r--src/arch/mips/include/arch/cache.h4
-rw-r--r--src/arch/mips/include/arch/cpu.h7
2 files changed, 7 insertions, 4 deletions
diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h
index 907505981b..3b89632dcd 100644
--- a/src/arch/mips/include/arch/cache.h
+++ b/src/arch/mips/include/arch/cache.h
@@ -23,10 +23,6 @@
#include <stddef.h>
#include <stdint.h>
-#define get_icache_line() __get_line_size($16, 1, 19, 3)
-#define get_dcache_line() __get_line_size($16, 1, 10, 3)
-#define get_L2cache_line() __get_line_size($16, 2, 4, 4)
-
#define CACHE_TYPE_SHIFT (0)
#define CACHE_OP_SHIFT (2)
#define CACHE_TYPE_MASK (0x3)
diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h
index 957e427e73..e04621420e 100644
--- a/src/arch/mips/include/arch/cpu.h
+++ b/src/arch/mips/include/arch/cpu.h
@@ -106,6 +106,13 @@ do { \
#define read_c0_config1() __read_32bit_c0_register($16, 1)
#define write_c0_config1(val) __write_32bit_c0_register($16, 1, (val))
+#define read_c0_config2() __read_32bit_c0_register($16, 2)
+#define write_c0_config2(val) __write_32bit_c0_register($16, 2, (val))
+
+#define read_c0_l23taglo() __read_32bit_c0_register($28, 4)
+#define write_c0_l23taglo(val) __write_32bit_c0_register($28, 4, (val))
+
+
#define C0_ENTRYLO_PFN_SHIFT 6
#define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */
#define C0_ENTRYLO_D (0x1 << 2) /* Writeable */