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-rw-r--r--src/arch/riscv/Makefile.inc1
-rw-r--r--src/arch/riscv/arch_timer.c1
-rw-r--r--src/arch/riscv/boot.c1
-rw-r--r--src/arch/riscv/bootblock.S1
-rw-r--r--src/arch/riscv/fit_payload.c1
-rw-r--r--src/arch/riscv/fp_asm.S1
-rw-r--r--src/arch/riscv/include/arch/barrier.h1
-rw-r--r--src/arch/riscv/include/arch/boot.h1
-rw-r--r--src/arch/riscv/include/arch/byteorder.h1
-rw-r--r--src/arch/riscv/include/arch/cache.h1
-rw-r--r--src/arch/riscv/include/arch/cbconfig.h1
-rw-r--r--src/arch/riscv/include/arch/cpu.h1
-rw-r--r--src/arch/riscv/include/arch/encoding.h1
-rw-r--r--src/arch/riscv/include/arch/errno.h1
-rw-r--r--src/arch/riscv/include/arch/exception.h1
-rw-r--r--src/arch/riscv/include/arch/header.ld1
-rw-r--r--src/arch/riscv/include/arch/hlt.h1
-rw-r--r--src/arch/riscv/include/arch/memlayout.h1
-rw-r--r--src/arch/riscv/include/arch/mmio.h1
-rw-r--r--src/arch/riscv/include/arch/pmp.h1
-rw-r--r--src/arch/riscv/include/arch/smp/atomic.h1
-rw-r--r--src/arch/riscv/include/arch/smp/smp.h1
-rw-r--r--src/arch/riscv/include/arch/smp/spinlock.h1
-rw-r--r--src/arch/riscv/include/arch/stages.h1
-rw-r--r--src/arch/riscv/include/bits.h1
-rw-r--r--src/arch/riscv/include/mcall.h1
-rw-r--r--src/arch/riscv/include/sbi.h1
-rw-r--r--src/arch/riscv/include/vm.h1
-rw-r--r--src/arch/riscv/mcall.c1
-rw-r--r--src/arch/riscv/misaligned.c1
-rw-r--r--src/arch/riscv/misc.c1
-rw-r--r--src/arch/riscv/opensbi.c1
-rw-r--r--src/arch/riscv/payload.c1
-rw-r--r--src/arch/riscv/pmp.c1
-rw-r--r--src/arch/riscv/ramstage.S1
-rw-r--r--src/arch/riscv/romstage.c1
-rw-r--r--src/arch/riscv/sbi.c1
-rw-r--r--src/arch/riscv/smp.c1
-rw-r--r--src/arch/riscv/tables.c1
-rw-r--r--src/arch/riscv/trap_handler.c1
-rw-r--r--src/arch/riscv/trap_util.S1
-rw-r--r--src/arch/riscv/virtual_memory.c1
42 files changed, 0 insertions, 42 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 17f225a523..3c5d7e7cfa 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -1,7 +1,6 @@
################################################################################
##
## SPDX-License-Identifier: GPL-2.0-only
-## This file is part of the coreboot project.
##
################################################################################
diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c
index af5db5ed61..7e9072b6cd 100644
--- a/src/arch/riscv/arch_timer.c
+++ b/src/arch/riscv/arch_timer.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <device/mmio.h>
#include <arch/encoding.h>
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index 0e6e2233f2..7cb0a3636f 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <program_loading.h>
#include <vm.h>
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index b25a541949..12fda328f6 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/*
* Early initialization code for RISC-V
*/
diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c
index 58d40f3959..32090889fd 100644
--- a/src/arch/riscv/fit_payload.c
+++ b/src/arch/riscv/fit_payload.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* This file is part of the coreboot project. */
#include <cbfs.h>
#include <commonlib/bsd/compression.h>
diff --git a/src/arch/riscv/fp_asm.S b/src/arch/riscv/fp_asm.S
index 5961047aa9..4bc86cfc33 100644
--- a/src/arch/riscv/fp_asm.S
+++ b/src/arch/riscv/fp_asm.S
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/*
* This file define some function used to swap value between memory
diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h
index d5e61e8b47..798f879a32 100644
--- a/src/arch/riscv/include/arch/barrier.h
+++ b/src/arch/riscv/include/arch/barrier.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* This file is part of the coreboot project. */
#ifndef __ARCH_BARRIER_H_
#define __ARCH_BARRIER_H__
diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h
index be1e6f1ce3..097022e2a7 100644
--- a/src/arch/riscv/include/arch/boot.h
+++ b/src/arch/riscv/include/arch/boot.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H
#define ARCH_RISCV_INCLUDE_ARCH_BOOT_H
diff --git a/src/arch/riscv/include/arch/byteorder.h b/src/arch/riscv/include/arch/byteorder.h
index 096ef7585a..2485358044 100644
--- a/src/arch/riscv/include/arch/byteorder.h
+++ b/src/arch/riscv/include/arch/byteorder.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef _BYTEORDER_H
#define _BYTEORDER_H
diff --git a/src/arch/riscv/include/arch/cache.h b/src/arch/riscv/include/arch/cache.h
index b42ad95ea0..0f3bc8be1f 100644
--- a/src/arch/riscv/include/arch/cache.h
+++ b/src/arch/riscv/include/arch/cache.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* This file is part of the coreboot project. */
#ifndef ARCH_CACHE_H
#define ARCH_CACHE_H
diff --git a/src/arch/riscv/include/arch/cbconfig.h b/src/arch/riscv/include/arch/cbconfig.h
index fedc8bdcc6..27812dec11 100644
--- a/src/arch/riscv/include/arch/cbconfig.h
+++ b/src/arch/riscv/include/arch/cbconfig.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef _ARCH_CBCONFIG_H_
#define _ARCH_CBCONFIG_H_
diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index e249aa3964..d623e84241 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef __ARCH_CPU_H__
#define __ARCH_CPU_H__
diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h
index 8aae565ba0..4f01e5ce97 100644
--- a/src/arch/riscv/include/arch/encoding.h
+++ b/src/arch/riscv/include/arch/encoding.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-4-Clause-UC */
-/* This file is part of the coreboot project. */
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
diff --git a/src/arch/riscv/include/arch/errno.h b/src/arch/riscv/include/arch/errno.h
index 1aa8eebb87..c3edc15e43 100644
--- a/src/arch/riscv/include/arch/errno.h
+++ b/src/arch/riscv/include/arch/errno.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-4-Clause-UC */
-/* This file is part of the coreboot project. */
#ifndef _RISCV_ERRNO_BASE_H
#define _RISCV_ERRNO_BASE_H
diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h
index 3e8da6c0f4..208cc81e24 100644
--- a/src/arch/riscv/include/arch/exception.h
+++ b/src/arch/riscv/include/arch/exception.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* This file is part of the coreboot project. */
#ifndef _ARCH_EXCEPTION_H
#define _ARCH_EXCEPTION_H
diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld
index 1168b37b8c..d8147728ee 100644
--- a/src/arch/riscv/include/arch/header.ld
+++ b/src/arch/riscv/include/arch/header.ld
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <rules.h>
diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h
index 4020defe30..bdefbb5de7 100644
--- a/src/arch/riscv/include/arch/hlt.h
+++ b/src/arch/riscv/include/arch/hlt.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
static __always_inline void hlt(void)
{
diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h
index fcbe6a7042..3a77bd527b 100644
--- a/src/arch/riscv/include/arch/memlayout.h
+++ b/src/arch/riscv/include/arch/memlayout.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/* This file contains macro definitions for memlayout.ld linker scripts. */
diff --git a/src/arch/riscv/include/arch/mmio.h b/src/arch/riscv/include/arch/mmio.h
index e66629e4ad..e2dbce4ab6 100644
--- a/src/arch/riscv/include/arch/mmio.h
+++ b/src/arch/riscv/include/arch/mmio.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef __ARCH_MMIO_H__
#define __ARCH_MMIO_H__
diff --git a/src/arch/riscv/include/arch/pmp.h b/src/arch/riscv/include/arch/pmp.h
index 8335349e4f..663e50a97f 100644
--- a/src/arch/riscv/include/arch/pmp.h
+++ b/src/arch/riscv/include/arch/pmp.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef __RISCV_PMP_H__
#define __RISCV_PMP_H__
diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h
index 1ac6e79a9a..ba20efbc64 100644
--- a/src/arch/riscv/include/arch/smp/atomic.h
+++ b/src/arch/riscv/include/arch/smp/atomic.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-4-Clause-UC */
-/* This file is part of the coreboot project. */
#ifndef _RISCV_ATOMIC_H
#define _RISCV_ATOMIC_H
diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h
index 353f8f5f36..9d3ae5f92b 100644
--- a/src/arch/riscv/include/arch/smp/smp.h
+++ b/src/arch/riscv/include/arch/smp/smp.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef _RISCV_SMP_H
#define _RISCV_SMP_H
diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h
index c9c2e6c02b..b316ff078d 100644
--- a/src/arch/riscv/include/arch/smp/spinlock.h
+++ b/src/arch/riscv/include/arch/smp/spinlock.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef ARCH_SMP_SPINLOCK_H
#define ARCH_SMP_SPINLOCK_H
diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h
index 2d8166894f..f9de2b5502 100644
--- a/src/arch/riscv/include/arch/stages.h
+++ b/src/arch/riscv/include/arch/stages.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef __ARCH_STAGES_H
#define __ARCH_STAGES_H
diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h
index 8afb14a5d7..26f8663cb3 100644
--- a/src/arch/riscv/include/bits.h
+++ b/src/arch/riscv/include/bits.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-4-Clause-UC */
-/* This file is part of the coreboot project. */
#ifndef _BITS_H
#define _BITS_H
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index 44b2d27334..803ee3e66b 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef _MCALL_H
#define _MCALL_H
diff --git a/src/arch/riscv/include/sbi.h b/src/arch/riscv/include/sbi.h
index 2905310b88..04b0ac7c3f 100644
--- a/src/arch/riscv/include/sbi.h
+++ b/src/arch/riscv/include/sbi.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef RISCV_SBI_H
#define RISCV_SBI_H
diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h
index 5c2b1d4f6a..5501a0c710 100644
--- a/src/arch/riscv/include/vm.h
+++ b/src/arch/riscv/include/vm.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-4-Clause-UC */
-/* This file is part of the coreboot project. */
#ifndef _VM_H
#define _VM_H
diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c
index 8e788a7c70..7f846bd83e 100644
--- a/src/arch/riscv/mcall.c
+++ b/src/arch/riscv/mcall.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: BSD-4-Clause-UC */
-/* This file is part of the coreboot project. */
#include <mcall.h>
#include <string.h>
diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c
index 172b21524c..eff51fc96e 100644
--- a/src/arch/riscv/misaligned.c
+++ b/src/arch/riscv/misaligned.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stddef.h>
#include <stdint.h>
diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c
index 71bef1d787..9054ffd972 100644
--- a/src/arch/riscv/misc.c
+++ b/src/arch/riscv/misc.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <delay.h>
diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c
index d9fdc2fb8e..e719560db3 100644
--- a/src/arch/riscv/opensbi.c
+++ b/src/arch/riscv/opensbi.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <sbi/fw_dynamic.h>
#include <arch/boot.h>
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index 715d7f378c..3097ad1bf8 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <program_loading.h>
#include <stdint.h>
diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c
index e707051a85..ee39ac44dc 100644
--- a/src/arch/riscv/pmp.c
+++ b/src/arch/riscv/pmp.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <arch/encoding.h>
#include <stdint.h>
diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S
index 676c59ba1f..921c46d8a5 100644
--- a/src/arch/riscv/ramstage.S
+++ b/src/arch/riscv/ramstage.S
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <arch/encoding.h>
#include <bits.h>
diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c
index 0991c681b4..5146b0e55f 100644
--- a/src/arch/riscv/romstage.c
+++ b/src/arch/riscv/romstage.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/*
* Entry points must be placed at the location the previous stage jumps
diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
index bbde935ea9..38fc05e210 100644
--- a/src/arch/riscv/sbi.c
+++ b/src/arch/riscv/sbi.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <mcall.h>
#include <stdint.h>
diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
index eb435d85a4..b3e13ff9fb 100644
--- a/src/arch/riscv/smp.c
+++ b/src/arch/riscv/smp.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stddef.h>
#include <arch/encoding.h>
diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c
index 8a60b43e62..4935ef5ece 100644
--- a/src/arch/riscv/tables.c
+++ b/src/arch/riscv/tables.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <bootmem.h>
#include <boot/tables.h>
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 91db11479b..32b2c409f7 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/*
* Early initialization code for riscv
*/
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 0e7d53bfcf..f1c4c4d3b8 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/*
* Early initialization code for riscv
*/
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 431f711ba3..467b93de16 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/*
* Early initialization code for riscv virtual memory
*/