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-rw-r--r--src/arch/riscv/bootblock.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 81a4455d97..95e1923ce2 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -24,6 +24,12 @@
.global _estack
.globl _start
_start:
+ csrr a0, mhartid
+ li a3, 0
+ beq a0, a3, _hart_zero
+_hart_loop:
+ j _hart_loop
+_hart_zero:
# The boot ROM may pass the following arguments to coreboot:
# a0: the value of mhartid