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-rw-r--r--src/arch/x86/assembly_entry.S25
1 files changed, 0 insertions, 25 deletions
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 9d6f5a42b4..fef5ce9240 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -13,8 +13,6 @@
#include <rules.h>
-#if !CONFIG(ROMCC_BOOTBLOCK)
-
/*
* This path is for stages that are post bootblock. The gdt is reloaded
* to accommodate platforms that are executing out of CAR. In order to
@@ -60,26 +58,3 @@ debug_spinloop:
/* Expect to never return. */
1:
jmp 1b
-
-#else
-
-/* This file assembles the start of the romstage program by the order of the
- * includes. Thus, it's extremely important that one pays very careful
- * attention to the order of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/32bit/entry32.inc>
-#include <cpu/x86/fpu_enable.inc>
-#if CONFIG(SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
-
-/*
- * The assembly.inc is generated based on the requirements of the mainboard.
- * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
- * processed by ROMCC and added. In non-ROMCC boards the chipsets'
- * cache-as-ram setup files would be here.
- */
-#include <generated/assembly.inc>
-
-#endif