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-rw-r--r--src/arch/x86/include/arch/cache.h7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h
index 9f7cda2643..c0d50e650d 100644
--- a/src/arch/x86/include/arch/cache.h
+++ b/src/arch/x86/include/arch/cache.h
@@ -34,13 +34,6 @@
#include <arch/early_variables.h>
#include <cpu/x86/cache.h>
-/*
- * For the purposes of the currently executing CPU loading code that will be
- * run there aren't any cache coherency operations required. This just provides
- * symmetry between architectures.
- */
-static inline void cache_sync_instructions(void) {}
-
/* Executing WBINVD when running out of CAR would not be good, prevent that. */
static inline void dcache_clean_invalidate_all(void)
{