diff options
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/Kconfig | 5 | ||||
| -rw-r--r-- | src/arch/x86/Makefile.inc | 25 | ||||
| -rw-r--r-- | src/arch/x86/exit_car.S | 106 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/cpu.h | 37 | ||||
| -rw-r--r-- | src/arch/x86/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/arch/x86/postcar_loader.c | 115 |
6 files changed, 290 insertions, 0 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4102b6805f..724c4dba61 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -167,3 +167,8 @@ config ROMSTAGE_ADDR config VERSTAGE_ADDR hex default 0x2000000 + +# Use the post CAR infrastructure for tearing down cache-as-ram +# from a program loaded in ram and subsequently loading ramstage. +config POSTCAR_STAGE + def_bool n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1ba879573e..10664c3ba3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -331,6 +331,7 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) +romstage-$(CONFIG_POSTCAR_STAGE) += postcar_loader.c romstage-y += cbmem.c romstage-y += boot.c @@ -390,3 +391,27 @@ rmodules_x86_64-y += memmove.c endif endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 + +$(eval $(call create_class_compiler,postcar,x86_32)) +postcar-generic-ccopts += -D__POSTCAR__ + +postcar-y += boot.c +postcar-y += cbfs_and_run.c +postcar-y += exit_car.S +postcar-y += memset.c +postcar-y += memcpy.c +postcar-y += memmove.c +postcar-y += memlayout.ld +postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c + +$(objcbfs)/postcar.debug: $$(postcar-objs) + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) + +$(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod + cp $< $@ + +cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar +$(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf +$(CONFIG_CBFS_PREFIX)/postcar-type := stage +$(CONFIG_CBFS_PREFIX)/postcar-compression := none diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S new file mode 100644 index 0000000000..e04bd04b25 --- /dev/null +++ b/src/arch/x86/exit_car.S @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> + +.section ".module_parameters", "aw", @progbits +/* stack_top indicates the stack to pull MTRR information from. */ +stack_top: +.long 0 +.long 0 + +.text +.global _start +_start: + /* chipset_teardown_car() is expected to disable cache-as-ram. */ + call chipset_teardown_car + + /* Enable caching if not already enabled. */ + mov %cr0, %eax + and $(~(CR0_CD | CR0_NW)), %eax + mov %eax, %cr0 + + /* Ensure cache is clean. */ + invd + + /* Set up new stack. */ + mov stack_top, %esp + + /* + * Honor variable MTRR information pushed on the stack with the + * following layout: + * + * Offset: Value + * ... + * 0x14: MTRR mask 0 63:32 + * 0x10: MTRR mask 0 31:0 + * 0x0c: MTRR base 0 63:32 + * 0x08: MTRR base 0 31:0 + * 0x04: Number of variable MTRRs to set + * 0x00: Number of variable MTRRs to clear + */ + + /* Clear variable MTRRs. */ + pop %ebx /* Number to clear */ + test %ebx, %ebx + jz 2f + xor %eax, %eax + xor %edx, %edx + mov $(MTRR_PHYS_BASE(0)), %ecx +1: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz 1b +2: + + /* Set Variable MTRRs based on stack contents. */ + pop %ebx /* Number to set. */ + test %ebx, %ebx + jz 2f + mov $(MTRR_PHYS_BASE(0)), %ecx +1: + /* Write MTRR base. */ + pop %eax + pop %edx + wrmsr + inc %ecx + /* Write MTRR mask. */ + pop %eax + pop %edx + wrmsr + inc %ecx + + dec %ebx + jnz 1b +2: + + /* Enable MTRR. */ + mov $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + /* Make default type uncacheable. */ + and $(~(MTRR_DEF_TYPE_MASK)), %eax + or $(MTRR_DEF_TYPE_EN), %eax + wrmsr + + /* Load and run ramstage. */ + call copy_and_run + /* Should never return. */ +1: + jmp 1b diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index f50901fe73..5c26bcf74d 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -15,6 +15,7 @@ #define ARCH_CPU_H #include <stdint.h> +#include <stddef.h> #include <rules.h> /* @@ -246,6 +247,42 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) * cache-as-ram. */ void asmlinkage car_stage_entry(void); + +/* + * Support setting up a stack frame consisting of MTRR information + * for use in bootstrapping the caching attributes after cache-as-ram + * is torn down. + */ + +struct postcar_frame { + uintptr_t stack; + uint32_t upper_mask; + int max_var_mttrs; + int num_var_mttrs; +}; + +/* + * Initialize postcar_frame object allocating stack size in cbmem + * with the provided size. Returns 0 on success, < 0 on error. + */ +int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); + +/* + * Add variable MTRR covering the provided range with MTRR type. + */ +void postcar_frame_add_mtrr(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type); + +/* + * Load and run a program that takes control of execution that + * tears down CAR and loads ramstage. The postcar_frame object + * indicates how to set up the frame. If caching is enabled at + * the time of the call it is up to the platform code to handle + * coherency with dirty lines in the cache using some mechansim + * such as platform_prog_run() because run_postcar_phase() + * utilizes prog_run() internally. + */ +void run_postcar_phase(struct postcar_frame *pcf); #endif #endif /* ARCH_CPU_H */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 5661104179..e6db0b8fe6 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -51,6 +51,8 @@ SECTIONS /* Pull in the cache-as-ram rules. */ #include "car.ld" +#elif ENV_POSTCAR + POSTCAR(32M, 1M) #endif } diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c new file mode 100644 index 0000000000..580cc4585c --- /dev/null +++ b/src/arch/x86/postcar_loader.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <program_loading.h> +#include <rmodule.h> + +static inline void stack_push(struct postcar_frame *pcf, uint32_t val) +{ + uint32_t *ptr; + + pcf->stack -= sizeof(val); + ptr = (void *)pcf->stack; + *ptr = val; +} + +int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) +{ + void *stack; + msr_t msr; + + msr = rdmsr(MTRR_CAP_MSR); + + stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size); + if (stack == NULL) { + printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n", + stack_size); + return -1; + } + + pcf->stack = (uintptr_t)stack; + pcf->stack += stack_size; + + pcf->upper_mask = (1 << (cpu_phys_address_size() - 32)) - 1; + + pcf->max_var_mttrs = msr.lo & MTRR_CAP_VCNT; + + pcf->num_var_mttrs = 0; + + return 0; +} + +void postcar_frame_add_mtrr(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type) +{ + size_t align; + + if (pcf->num_var_mttrs >= pcf->max_var_mttrs) { + printk(BIOS_ERR, "No more variable MTRRs: %d\n", + pcf->max_var_mttrs); + return; + } + + /* Determine address alignment by lowest bit set in address. */ + align = addr & (addr ^ (addr - 1)); + + if (align < size) { + printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n", + addr, align, size); + size = align; + } + + /* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */ + stack_push(pcf, pcf->upper_mask); + stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID); + stack_push(pcf, 0); + stack_push(pcf, addr | type); + pcf->num_var_mttrs++; +} + +void run_postcar_phase(struct postcar_frame *pcf) +{ + struct prog prog = + PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); + struct rmod_stage_load rsl = { + .cbmem_id = CBMEM_ID_AFTER_CAR, + .prog = &prog, + }; + + /* + * Place the number of used variable MTRRs on stack then max number + * of variable MTRRs supported in the system. + */ + stack_push(pcf, pcf->num_var_mttrs); + stack_push(pcf, pcf->max_var_mttrs); + + if (prog_locate(&prog)) + die("Failed to locate after CAR program.\n"); + if (rmodule_stage_load(&rsl)) + die("Failed to load after CAR program.\n"); + + /* Set the stack pointer within parameters of the program loaded. */ + if (rsl.params == NULL) + die("No parameters found in after CAR program.\n"); + + *(uintptr_t *)rsl.params = pcf->stack; + + prog_run(&prog); +} |