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-rw-r--r--src/arch/arm/include/armv7/arch/cache.h4
-rw-r--r--src/arch/arm64/include/armv8/arch/cache.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index dd271c5bce..9a8021761e 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -48,8 +48,8 @@
#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
#define SCTLR_Z (1 << 11) /* Branch prediction enable */
#define SCTLR_I (1 << 12) /* Instruction cache enable */
-#define SCTLR_V (1 << 13) /* Low/high exception vectors */
-#define SCTLR_RR (1 << 14) /* Round Robin select */
+#define SCTLR_V (1 << 13) /* Low/high exception vectors */
+#define SCTLR_RR (1 << 14) /* Round Robin select */
/* Bits 16:15 are reserved */
#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
/* Bit 18 is reserved */
diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h
index b31c3b0153..8e133efcff 100644
--- a/src/arch/arm64/include/armv8/arch/cache.h
+++ b/src/arch/arm64/include/armv8/arch/cache.h
@@ -48,8 +48,8 @@
#define SCTLR_EL1_UMA (1 << 9) /* User mask access */
#define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */
#define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */
-#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */
-#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */
+#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */
+#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */
#define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */
#define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */