diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/armv7/include/arch/rules.h | 34 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/cpu.h | 12 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/io.h | 6 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/pci_ops.h | 4 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/rules.h | 34 |
5 files changed, 83 insertions, 7 deletions
diff --git a/src/arch/armv7/include/arch/rules.h b/src/arch/armv7/include/arch/rules.h new file mode 100644 index 0000000000..a790365118 --- /dev/null +++ b/src/arch/armv7/include/arch/rules.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__PRE_RAM__) +#define __SIMPLE_DEVICE__ +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 6944834169..3e50be4234 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -2,6 +2,7 @@ #define ARCH_CPU_H #include <stdint.h> +#include <arch/rules.h> /* * EFLAGS bits @@ -141,12 +142,13 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> - int cpu_phys_address_size(void); int cpu_have_cpuid(void); +#ifndef __SIMPLE_DEVICE__ + +struct device; + struct cpu_device_id { unsigned vendor; unsigned device; @@ -163,7 +165,7 @@ struct cpu_driver *find_cpu_driver(struct device *cpu); struct thread; struct cpu_info { - device_t cpu; + struct device *cpu; unsigned int index; #if CONFIG_COOP_MULTITASKING struct thread *thread; @@ -188,8 +190,6 @@ static inline unsigned long cpu_index(void) ci = cpu_info(); return ci->index; } -#else -#include <arch/io.h> #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index b258dd0163..3b61e85b07 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -2,6 +2,7 @@ #define _ASM_IO_H #include <stdint.h> +#include <arch/rules.h> /* * This file contains the definitions for the x86 IO instructions @@ -188,6 +189,9 @@ static inline int log2f(int value) return r; } +#endif + +#ifdef __SIMPLE_DEVICE__ #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ (((SEGBUS) & 0xFFF) << 20) | \ @@ -325,7 +329,7 @@ static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsi pnp_write_config(dev, index, drq & 0xff); } -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ #endif diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index b7ec0ba8d8..e1b148b02a 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -1,6 +1,8 @@ #ifndef ARCH_I386_PCI_OPS_H #define ARCH_I386_PCI_OPS_H +#ifndef __SIMPLE_DEVICE__ + extern const struct pci_bus_operations pci_cf8_conf1; #if CONFIG_MMCONF_SUPPORT @@ -9,4 +11,6 @@ extern const struct pci_bus_operations pci_ops_mmconf; const struct pci_bus_operations *pci_bus_default_ops(device_t dev); +#endif + #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h new file mode 100644 index 0000000000..4b8467730d --- /dev/null +++ b/src/arch/x86/include/arch/rules.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__PRE_RAM__) || defined(__SMM__) +#define __SIMPLE_DEVICE__ +#endif + +#endif /* _ARCH_RULES_H */ |