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-rw-r--r--src/arch/i386/Config.lb4
-rw-r--r--src/arch/i386/include/arch/acpi.h2
-rw-r--r--src/arch/i386/include/arch/ioapic.h46
-rw-r--r--src/arch/i386/smp/Config.lb6
-rw-r--r--src/arch/i386/smp/Makefile.inc3
-rw-r--r--src/arch/i386/smp/ioapic.c206
6 files changed, 180 insertions, 87 deletions
diff --git a/src/arch/i386/Config.lb b/src/arch/i386/Config.lb
index 3b5be31d91..7234c3324b 100644
--- a/src/arch/i386/Config.lb
+++ b/src/arch/i386/Config.lb
@@ -70,6 +70,4 @@ end
dir lib
dir boot
-if CONFIG_SMP
- dir smp
-end
+dir smp
diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h
index 21ec64e96e..67d993de12 100644
--- a/src/arch/i386/include/arch/acpi.h
+++ b/src/arch/i386/include/arch/acpi.h
@@ -425,8 +425,6 @@ do { \
gsi_base+=4; \
} while(0);
-#define IO_APIC_ADDR 0xfec00000UL
-
#else // CONFIG_GENERATE_ACPI_TABLES
#define write_acpi_tables(start) (start)
diff --git a/src/arch/i386/include/arch/ioapic.h b/src/arch/i386/include/arch/ioapic.h
new file mode 100644
index 0000000000..ceca32c91c
--- /dev/null
+++ b/src/arch/i386/include/arch/ioapic.h
@@ -0,0 +1,46 @@
+/*
+ * coreboot IOAPIC support
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __I386_ARCH_IOAPIC_H
+#define __I386_ARCH_IOAPIC_H
+
+#define IO_APIC_ADDR 0xfec00000UL
+#define IO_APIC_INTERRUPTS 24
+
+#define ALL (0xff << 24)
+#define NONE (0)
+#define DISABLED (1 << 16)
+#define ENABLED (0 << 16)
+#define TRIGGER_EDGE (0 << 15)
+#define TRIGGER_LEVEL (1 << 15)
+#define POLARITY_HIGH (0 << 13)
+#define POLARITY_LOW (1 << 13)
+#define PHYSICAL_DEST (0 << 11)
+#define LOGICAL_DEST (1 << 11)
+#define ExtINT (7 << 8)
+#define NMI (4 << 8)
+#define SMI (2 << 8)
+#define INT (1 << 8)
+
+void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
+void clear_ioapic(u32 ioapic_base);
+
+#endif
diff --git a/src/arch/i386/smp/Config.lb b/src/arch/i386/smp/Config.lb
index cfbac7b552..70981a9e78 100644
--- a/src/arch/i386/smp/Config.lb
+++ b/src/arch/i386/smp/Config.lb
@@ -1,8 +1,10 @@
uses CONFIG_GENERATE_MP_TABLE
+uses CONFIG_IOAPIC
if CONFIG_GENERATE_MP_TABLE
object mpspec.o
end
-#object ioapic.o CONFIG_IOAPIC
-
+if CONFIG_IOAPIC
+ object ioapic.o
+end
diff --git a/src/arch/i386/smp/Makefile.inc b/src/arch/i386/smp/Makefile.inc
index 27e1291e49..44190587b9 100644
--- a/src/arch/i386/smp/Makefile.inc
+++ b/src/arch/i386/smp/Makefile.inc
@@ -1,4 +1,3 @@
obj-$(CONFIG_GENERATE_MP_TABLE) += mpspec.o
-# what about this: how awkward.
-#object ioapic.o CONFIG_IOAPIC
+obj-$(CONFIG_IOAPIC) += ioapic.o
diff --git a/src/arch/i386/smp/ioapic.c b/src/arch/i386/smp/ioapic.c
index d64b0ad3f3..630463e63d 100644
--- a/src/arch/i386/smp/ioapic.c
+++ b/src/arch/i386/smp/ioapic.c
@@ -1,85 +1,135 @@
-#include <console/console.h>
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
#include <arch/ioapic.h>
+#include <console/console.h>
+#include <cpu/x86/lapic.h>
-/* we have to do more than we thought. I assumed Linux would do all the
- * interesting parts, and I was wrong.
- */
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* mask, trigger, polarity, destination, delivery, vector */
- {0x00, DISABLED, NONE},
- {0x01, DISABLED, NONE},
- {0x02, DISABLED, NONE},
- {0x03, DISABLED, NONE},
- {0x04, DISABLED, NONE},
- {0x05, DISABLED, NONE},
- {0x06, DISABLED, NONE},
- {0x07, DISABLED, NONE},
- {0x08, DISABLED, NONE},
- {0x09, DISABLED, NONE},
- {0x0a, DISABLED, NONE},
- {0x0b, DISABLED, NONE},
- {0x0c, DISABLED, NONE},
- {0x0d, DISABLED, NONE},
- {0x0e, DISABLED, NONE},
- {0x0f, DISABLED, NONE},
- {0x10, DISABLED, NONE},
- {0x11, DISABLED, NONE},
- {0x12, DISABLED, NONE},
- {0x13, DISABLED, NONE},
- {0x14, DISABLED, NONE},
- {0x14, DISABLED, NONE},
- {0x15, DISABLED, NONE},
- {0x16, DISABLED, NONE},
- {0x17, DISABLED, NONE},
-};
-
-void setup_ioapic(void)
+static u32 io_apic_read(u32 ioapic_base, u32 reg)
+{
+ write32(ioapic_base, reg);
+ return read32(ioapic_base + 0x10);
+}
+
+static void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
+{
+ write32(ioapic_base, reg);
+ write32(ioapic_base + 0x10, value);
+}
+
+
+void clear_ioapic(u32 ioapic_base)
+{
+ u32 low, high;
+ u32 i, ioapic_interrupts;
+
+ printk_debug("IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
+
+ /* Read the available number of interrupts */
+ ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
+ if (!ioapic_interrupts || ioapic_interrupts == 0xff)
+ ioapic_interrupts = 24;
+ printk_debug("IOAPIC: %d interrupts\n", ioapic_interrupts);
+
+ low = DISABLED;
+ high = NONE;
+
+ for (i = 0; i < ioapic_interrupts; i++) {
+ io_apic_write(ioapic_base, i * 2 + 0x10, low);
+ io_apic_write(ioapic_base, i * 2 + 0x11, high);
+
+ printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+ }
+
+ if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
+ printk_warning("IO APIC not responding.\n");
+ return;
+ }
+}
+
+void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapicaddr = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
-
- l = (unsigned long *) ioapicaddr;
-#if defined(i786)
- /* For the pentium 4 and above apic deliver their interrupts
+ u32 bsp_lapicid = lapicid();
+ u32 low, high;
+ u32 i, ioapic_interrupts;
+
+ printk_debug("IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base);
+ printk_debug("IOAPIC: Bootstrap Processor Local APIC = %02x\n",
+ bsp_lapicid);
+
+ if (ioapic_id) {
+ printk_debug("IOAPIC: ID = 0x%02x\n", ioapic_id);
+ /* Set IOAPIC ID if it has been specified */
+ io_apic_write(ioapic_base, 0x00,
+ (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) |
+ (ioapic_id << 24));
+ }
+
+ /* Read the available number of interrupts */
+ ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
+ if (!ioapic_interrupts || ioapic_interrupts == 0xff)
+ ioapic_interrupts = 24;
+ printk_debug("IOAPIC: %d interrupts\n", ioapic_interrupts);
+
+
+// XXX this decision should probably be made elsewhere, and
+// it's the C3, not the EPIA this depends on.
+#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT
+#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+#else
+#define IOAPIC_INTERRUPTS_ON_FSB
+#endif
+
+#ifdef IOAPIC_INTERRUPTS_ON_FSB
+ /* For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that.
*/
- l[0] = 0x03;
- l[4] = 1;
-#endif /* i786 */
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
+ printk_debug("IOAPIC: Enabling interrupts on FSB\n");
+ io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0));
+#endif
+#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+ printk_debug("IOAPIC: Enabling interrupts on APIC serial bus\n");
+ io_apic_write(ioapic_base, 0x03, 0);
+#endif
+
+ /* Enable Virtual Wire Mode */
+ low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
+ high = bsp_lapicid << (56 - 32);
+
+ io_apic_write(ioapic_base, 0x10, low);
+ io_apic_write(ioapic_base, 0x11, high);
+
+ if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
+ printk_warning("IO APIC not responding.\n");
+ return;
+ }
+
+ printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
+
+ low = DISABLED;
+ high = NONE;
+
+ for (i = 1; i < ioapic_interrupts; i++) {
+ io_apic_write(ioapic_base, i * 2 + 0x10, low);
+ io_apic_write(ioapic_base, i * 2 + 0x11, high);
+
+ printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
}
}
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