diff options
Diffstat (limited to 'src/arch')
36 files changed, 204 insertions, 204 deletions
diff --git a/src/arch/i386/boot/acpi.c b/src/arch/i386/boot/acpi.c index 9bab92831f..e5169eaf43 100644 --- a/src/arch/i386/boot/acpi.c +++ b/src/arch/i386/boot/acpi.c @@ -7,7 +7,7 @@ * Copyright (C) 2004 SUSE LINUX AG * Copyright (C) 2005-2009 coresystems GmbH * - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9@btinternet.com>, and those portions * Copyright (C) 2004 Nick Barker * @@ -15,12 +15,12 @@ * 2005.9 yhlu add SRAT table generation */ -/* +/* * Each system port implementing ACPI has to provide two functions: - * + * * write_acpi_tables() * acpi_dump_apics() - * + * * See Kontron 986LCD-M port for a good example of an ACPI implementation * in coreboot. */ @@ -59,10 +59,10 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) if (rsdp->xsdt_address) { xsdt = (acpi_xsdt_t *)((u32)rsdp->xsdt_address); } - + /* This should always be MAX_ACPI_TABLES */ entries_num = ARRAY_SIZE(rsdt->entry); - + for (i = 0; i < entries_num; i++) { if(rsdt->entry[i] == 0) break; @@ -120,10 +120,10 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) lapic->type=0; lapic->length=sizeof(acpi_madt_lapic_t); lapic->flags=1; - + lapic->processor_id=cpu; lapic->apic_id=apic; - + return(lapic->length); } @@ -146,16 +146,16 @@ unsigned long acpi_create_madt_lapics(unsigned long current) return current; } -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base) +int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base) { ioapic->type=1; ioapic->length=sizeof(acpi_madt_ioapic_t); ioapic->reserved=0x00; ioapic->gsi_base=gsi_base; - + ioapic->ioapic_id=id; ioapic->ioapic_addr=addr; - + return(ioapic->length); } @@ -168,7 +168,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, irqoverride->source=source; irqoverride->gsirq=gsirq; irqoverride->flags=flags; - + return(irqoverride->length); } @@ -177,29 +177,29 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, { lapic_nmi->type=4; lapic_nmi->length=sizeof(acpi_madt_lapic_nmi_t); - + lapic_nmi->flags=flags; lapic_nmi->processor_id=cpu; lapic_nmi->lint=lint; - + return(lapic_nmi->length); } void acpi_create_madt(acpi_madt_t *madt) { #define LOCAL_APIC_ADDR 0xfee00000ULL - + acpi_header_t *header=&(madt->header); unsigned long current=(unsigned long)madt+sizeof(acpi_madt_t); - + memset((void *)madt, 0, sizeof(acpi_madt_t)); - + /* fill out header fields */ memcpy(header->signature, "APIC", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_madt_t); header->revision = 1; @@ -207,10 +207,10 @@ void acpi_create_madt(acpi_madt_t *madt) madt->flags = 0x1; /* PCAT_COMPAT */ current = acpi_fill_madt(current); - + /* recalculate length */ header->length= current - (unsigned long)madt; - + header->checksum = acpi_checksum((void *)madt, header->length); } @@ -219,23 +219,23 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) acpi_header_t *header=&(mcfg->header); unsigned long current=(unsigned long)mcfg+sizeof(acpi_mcfg_t); - + memset((void *)mcfg, 0, sizeof(acpi_mcfg_t)); - + /* fill out header fields */ memcpy(header->signature, "MCFG", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_mcfg_t); header->revision = 1; current = acpi_fill_mcfg(current); - + /* recalculate length */ header->length= current - (unsigned long)mcfg; - + header->checksum = acpi_checksum((void *)mcfg, header->length); } @@ -294,7 +294,7 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, u32 mem->proximity_domain = node; - mem->flags = flags; + mem->flags = flags; return(mem->length); } @@ -356,15 +356,15 @@ void acpi_create_hpet(acpi_hpet_t *hpet) #define HPET_ADDR 0xfed00000ULL acpi_header_t *header=&(hpet->header); acpi_addr_t *addr=&(hpet->addr); - + memset((void *)hpet, 0, sizeof(acpi_hpet_t)); - + /* fill out header fields */ memcpy(header->signature, "HPET", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_hpet_t); header->revision = 1; @@ -378,12 +378,12 @@ void acpi_create_hpet(acpi_hpet_t *hpet) hpet->id = 0x102282a0; /* AMD ? */ hpet->number = 0; hpet->min_tick = 4096; - + header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } void acpi_create_facs(acpi_facs_t *facs) { - + memset( (void *)facs,0, sizeof(acpi_facs_t)); memcpy(facs->signature, "FACS", 4); @@ -398,46 +398,46 @@ void acpi_create_facs(acpi_facs_t *facs) } void acpi_write_rsdt(acpi_rsdt_t *rsdt) -{ +{ acpi_header_t *header=&(rsdt->header); - + /* fill out header fields */ memcpy(header->signature, "RSDT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_rsdt_t); header->revision = 1; - + /* fill out entries */ // entries are filled in later, we come with an empty set. - + /* fix checksum */ - + header->checksum = acpi_checksum((void *)rsdt, sizeof(acpi_rsdt_t)); } void acpi_write_xsdt(acpi_xsdt_t *xsdt) -{ +{ acpi_header_t *header=&(xsdt->header); - + /* fill out header fields */ memcpy(header->signature, "XSDT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_xsdt_t); header->revision = 1; - + /* fill out entries */ // entries are filled in later, we come with an empty set. - + /* fix checksum */ - + header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t)); } @@ -448,7 +448,7 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) memcpy(rsdp->oem_id, OEM_ID, 6); rsdp->length = sizeof(acpi_rsdp_t); rsdp->rsdt_address = (u32)rsdt; - /* Some OSes expect an XSDT to be present for RSD PTR + /* Some OSes expect an XSDT to be present for RSD PTR * revisions >= 2. If we don't have an ACPI XSDT, force * ACPI 1.0 (and thus RSD PTR revision 0) */ @@ -547,7 +547,7 @@ void *acpi_find_wakeup_vector(void) printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); rsdt = (acpi_rsdt_t *) rsdp->rsdt_address; - + end = (char *) rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end); diff --git a/src/arch/i386/boot/acpigen.c b/src/arch/i386/boot/acpigen.c index 3ed7a2f05d..2bd2ab5630 100644 --- a/src/arch/i386/boot/acpigen.c +++ b/src/arch/i386/boot/acpigen.c @@ -147,8 +147,8 @@ int acpigen_emit_stream(const char *data, int size) return size; } -/* The NameString are bit tricky, each element can be 4 chars, if - less its padded with underscore. Check 18.2.2 and 18.4 +/* The NameString are bit tricky, each element can be 4 chars, if + less its padded with underscore. Check 18.2.2 and 18.4 and 5.3 of ACPI specs 3.0 for details */ @@ -160,14 +160,14 @@ static int acpigen_emit_simple_namestring(const char *name) { len += acpigen_emit_stream(ud, 4 - i); break; } else { - len += acpigen_emit_byte(name[i]); + len += acpigen_emit_byte(name[i]); } } return len; } static int acpigen_emit_double_namestring(const char *name, int dotpos) { - int len = 0; + int len = 0; /* mark dual name prefix */ len += acpigen_emit_byte(0x2e); len += acpigen_emit_simple_namestring(name); @@ -177,7 +177,7 @@ static int acpigen_emit_double_namestring(const char *name, int dotpos) { static int acpigen_emit_multi_namestring(const char *name) { int len = 0, count = 0; - unsigned char *pathlen; + unsigned char *pathlen; /* mark multi name prefix */ len += acpigen_emit_byte(0x2f); len += acpigen_emit_byte(0x0); @@ -229,7 +229,7 @@ int acpigen_emit_namestring(const char *namepath) { if (dotcount == 0) { len += acpigen_emit_simple_namestring(namepath); - } else if (dotcount == 1) { + } else if (dotcount == 1) { len += acpigen_emit_double_namestring(namepath, dotpos); } else { len += acpigen_emit_multi_namestring(namepath); diff --git a/src/arch/i386/boot/boot.c b/src/arch/i386/boot/boot.c index 895065e64a..d9cb02e776 100644 --- a/src/arch/i386/boot/boot.c +++ b/src/arch/i386/boot/boot.c @@ -63,9 +63,9 @@ int elf_check_arch(Elf_ehdr *ehdr) return ( ((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) && (ehdr->e_ident[EI_CLASS] == ELFCLASS32) && - (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) + (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) ); - + } void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) @@ -74,7 +74,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) unsigned long lb_start, lb_size; unsigned long adjust, adjusted_boot_notes; - elf_boot_notes.hdr.b_checksum = + elf_boot_notes.hdr.b_checksum = compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); lb_start = (unsigned long)&_ram_seg; @@ -82,7 +82,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) adjust = buffer + size - lb_start; adjusted_boot_notes = (unsigned long)&elf_boot_notes; - adjusted_boot_notes += adjust; + adjusted_boot_notes += adjust; printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry); printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start); @@ -91,7 +91,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer); printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes); printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes); - + /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" @@ -172,7 +172,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) " popl %%edi\n\t" " popl %%esi\n\t" - :: + :: "ri" (lb_start), "ri" (buffer), "ri" (lb_size), "ri" (entry), #if CONFIG_MULTIBOOT diff --git a/src/arch/i386/boot/coreboot_table.c b/src/arch/i386/boot/coreboot_table.c index b88ca1adba..bdf3b1bc6a 100644 --- a/src/arch/i386/boot/coreboot_table.c +++ b/src/arch/i386/boot/coreboot_table.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2003-2004 Eric Biederman * Copyright (C) 2005-2010 coresystems GmbH * @@ -71,7 +71,7 @@ static struct lb_record *lb_last_record(struct lb_header *header) #if 0 static struct lb_record *lb_next_record(struct lb_record *rec) { - rec = (void *)(((char *)rec) + rec->size); + rec = (void *)(((char *)rec) + rec->size); return rec; } #endif @@ -173,7 +173,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) mainboard->tag = LB_TAG_MAINBOARD; mainboard->size = (sizeof(*mainboard) + - strlen(mainboard_vendor) + 1 + + strlen(mainboard_vendor) + 1 + strlen(mainboard_part_number) + 1 + 3) & ~3; @@ -203,7 +203,7 @@ static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; cmos_checksum->location = LB_CKS_LOC * 8; cmos_checksum->type = CHECKSUM_PCBIOS; - + return cmos_checksum; } #endif @@ -320,7 +320,7 @@ static void lb_cleanup_memory_ranges(struct lb_memory *mem) int entries; int i, j; entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - + /* Sort the lb memory ranges */ for(i = 0; i < entries; i++) { uint64_t entry_start = unpack_lb64(mem->map[i].start); @@ -357,17 +357,17 @@ static void lb_cleanup_memory_ranges(struct lb_memory *mem) mem->map[i].size = pack_lb64(end - start); /* Delete the entry I have merged with */ - memmove(&mem->map[i + 1], &mem->map[i + 2], + memmove(&mem->map[i + 1], &mem->map[i + 2], ((entries - i - 2) * sizeof(mem->map[0]))); mem->size -= sizeof(mem->map[0]); entries -= 1; /* See if I can merge with the next entry as well */ - i -= 1; + i -= 1; } } } -static void lb_remove_memory_range(struct lb_memory *mem, +static void lb_remove_memory_range(struct lb_memory *mem, uint64_t start, uint64_t size) { uint64_t end; @@ -383,16 +383,16 @@ static void lb_remove_memory_range(struct lb_memory *mem, uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); if ((start <= map_start) && (end >= map_end)) { /* Remove the completely covered range */ - memmove(&mem->map[i], &mem->map[i + 1], + memmove(&mem->map[i], &mem->map[i + 1], ((entries - i - 1) * sizeof(mem->map[0]))); mem->size -= sizeof(mem->map[0]); entries -= 1; /* Since the index will disappear revisit what will appear here */ - i -= 1; + i -= 1; } else if ((start > map_start) && (end < map_end)) { /* Split the memory range */ - memmove(&mem->map[i + 1], &mem->map[i], + memmove(&mem->map[i + 1], &mem->map[i], ((entries - i) * sizeof(mem->map[0]))); mem->size += sizeof(mem->map[0]); entries += 1; @@ -430,7 +430,7 @@ static void lb_dump_memory_ranges(struct lb_memory *mem) int entries; int i; entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - + printk(BIOS_DEBUG, "coreboot memory table:\n"); for(i = 0; i < entries; i++) { uint64_t entry_start = unpack_lb64(mem->map[i].start); @@ -448,14 +448,14 @@ static void lb_dump_memory_ranges(struct lb_memory *mem) default: entry_type="UNKNOWN!"; break; } - printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", + printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", i, entry_start, entry_start+entry_size-1, entry_type); - + } } -/* Routines to extract part so the coreboot table or +/* Routines to extract part so the coreboot table or * information from the coreboot table after we have written it. * Currently get_lb_mem relies on a global we can change the * implementaiton. @@ -492,8 +492,8 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) extern uint64_t high_tables_base, high_tables_size; #endif -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, +unsigned long write_coreboot_table( + unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) { struct lb_header *head; @@ -509,7 +509,7 @@ unsigned long write_coreboot_table( printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", rom_table_end); - + head = lb_table_init(rom_table_end); rom_table_end = (unsigned long)head; printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); @@ -523,7 +523,7 @@ unsigned long write_coreboot_table( low_table_end = (unsigned long)head; } #endif - + printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); low_table_end += 0xfff; // 4K aligned low_table_end &= ~0xfff; @@ -535,7 +535,7 @@ unsigned long write_coreboot_table( rom_table_end &= ~0xffff; printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); -#if (CONFIG_HAVE_OPTION_TABLE == 1) +#if (CONFIG_HAVE_OPTION_TABLE == 1) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a lb_record... */ @@ -546,9 +546,9 @@ unsigned long write_coreboot_table( #endif /* Record where RAM is located */ mem = build_lb_mem(head); - + /* Record the mptable and the the lb_table (This will be adjusted later) */ - lb_add_memory_range(mem, LB_MEM_TABLE, + lb_add_memory_range(mem, LB_MEM_TABLE, low_table_start, low_table_end - low_table_start); /* Record the pirq table, acpi tables, and maybe the mptable */ @@ -588,5 +588,5 @@ unsigned long write_coreboot_table( /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); - + } diff --git a/src/arch/i386/boot/mpspec.c b/src/arch/i386/boot/mpspec.c index 1beba873cc..47ad8ccb33 100644 --- a/src/arch/i386/boot/mpspec.c +++ b/src/arch/i386/boot/mpspec.c @@ -31,7 +31,7 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph { struct intel_mp_floating *mf; void *v; - + v = (void *)addr; mf = v; mf->mpf_signature[0] = '_'; @@ -106,7 +106,7 @@ void smp_write_processors(struct mp_config_table *mc) unsigned cpu_feature_flags; struct cpuid_result result; device_t cpu; - + boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; result = cpuid(1); @@ -114,7 +114,7 @@ void smp_write_processors(struct mp_config_table *mc) cpu_feature_flags = result.edx; for(cpu = all_devices; cpu; cpu = cpu->next) { unsigned long cpu_flag; - if ((cpu->path.type != DEVICE_PATH_APIC) || + if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { continue; @@ -126,7 +126,7 @@ void smp_write_processors(struct mp_config_table *mc) if (boot_apic_id == cpu->path.apic.apic_id) { cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; } - smp_write_processor(mc, + smp_write_processor(mc, cpu->path.apic.apic_id, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); @@ -146,7 +146,7 @@ void smp_write_bus(struct mp_config_table *mc, } void smp_write_ioapic(struct mp_config_table *mc, - unsigned char id, unsigned char ver, + unsigned char id, unsigned char ver, unsigned long apicaddr) { struct mpc_config_ioapic *mpc; diff --git a/src/arch/i386/boot/pirq_routing.c b/src/arch/i386/boot/pirq_routing.c index 86a3500444..4873f6d751 100644 --- a/src/arch/i386/boot/pirq_routing.c +++ b/src/arch/i386/boot/pirq_routing.c @@ -26,7 +26,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n", __func__, addr); - + sum = rt->checksum - sum; if (sum != rt->checksum) { @@ -72,9 +72,9 @@ static int verify_copy_pirq_routing_table(unsigned long addr) } } printk(BIOS_INFO, "done\n"); - + check_pirq_routing_table((struct irq_routing_table *)addr); - + return 0; } #endif diff --git a/src/arch/i386/boot/tables.c b/src/arch/i386/boot/tables.c index 76a7bb21b1..6ee7c2c876 100644 --- a/src/arch/i386/boot/tables.c +++ b/src/arch/i386/boot/tables.c @@ -60,12 +60,12 @@ struct lb_memory *write_tables(void) printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); - rom_table_start = 0xf0000; + rom_table_start = 0xf0000; rom_table_end = 0xf0000; /* Start low addr at 0x500, so we don't run into conflicts with the BDA * in case our data structures grow beyound 0x400. Only multiboot, GDT - * and the coreboot table use low_tables. + * and the coreboot table use low_tables. */ low_table_start = 0; low_table_end = 0x500; @@ -126,7 +126,7 @@ struct lb_memory *write_tables(void) /* Write ACPI tables to F segment and high tables area */ /* Ok, this is a bit hacky still, because some day we want to have this - * completely dynamic. But right now we are setting fixed sizes. + * completely dynamic. But right now we are setting fixed sizes. * It's probably still better than the old high_table_base code because * now at least we know when we have an overflow in the area. * @@ -213,7 +213,7 @@ struct lb_memory *write_tables(void) write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); } - + post_code(0x9e); #if CONFIG_HAVE_ACPI_RESUME @@ -223,7 +223,7 @@ struct lb_memory *write_tables(void) */ cbmem_add(CBMEM_ID_RESUME, 1024 * (1024-64)); #endif - + // Remove before sending upstream cbmem_list(); diff --git a/src/arch/i386/boot/wakeup.S b/src/arch/i386/boot/wakeup.S index b348e95a71..a1df4d5597 100644 --- a/src/arch/i386/boot/wakeup.S +++ b/src/arch/i386/boot/wakeup.S @@ -68,11 +68,11 @@ __wakeup: * protected mode is turned off. */ mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protection */ movl %cr0, %eax diff --git a/src/arch/i386/coreboot_ram.ld b/src/arch/i386/coreboot_ram.ld index 67c78cecbc..2e602205dd 100644 --- a/src/arch/i386/coreboot_ram.ld +++ b/src/arch/i386/coreboot_ram.ld @@ -59,7 +59,7 @@ SECTIONS . = ALIGN(4); _erodata = .; - } + } /* After the code we place initialized data (typically initialized * global variables). This gets copied into ram by startup code. * __data_start and __data_end shows where in ram this should be placed, @@ -113,11 +113,11 @@ SECTIONS /* Avoid running into 0xa0000-0xfffff */ _bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB"); - /* The ram segment. This includes all memory used by the memory + /* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on * the fly, but including stack and heap. */ - _ram_seg = _text; + _ram_seg = _text; _eram_seg = _eheap; /* CONFIG_RAMTOP is the upper address of cached memory (among other diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h index ebab54ca42..9b1e1a5d9e 100644 --- a/src/arch/i386/include/arch/acpi.h +++ b/src/arch/i386/include/arch/acpi.h @@ -30,7 +30,7 @@ #if CONFIG_GENERATE_ACPI_TABLES==1 #include <stdint.h> - + #define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" #define OEM_ID "CORE " diff --git a/src/arch/i386/include/arch/coreboot_tables.h b/src/arch/i386/include/arch/coreboot_tables.h index 91e6d6cbd5..3c9bf98f22 100644 --- a/src/arch/i386/include/arch/coreboot_tables.h +++ b/src/arch/i386/include/arch/coreboot_tables.h @@ -8,7 +8,7 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -void lb_memory_range(struct lb_memory *mem, +void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); /* Routines to extract part so the coreboot table or information diff --git a/src/arch/i386/include/arch/cpu.h b/src/arch/i386/include/arch/cpu.h index 30b6cc300b..3e799f014d 100644 --- a/src/arch/i386/include/arch/cpu.h +++ b/src/arch/i386/include/arch/cpu.h @@ -102,7 +102,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_RISE 7 #define X86_VENDOR_TRANSMETA 8 #define X86_VENDOR_NSC 9 -#define X86_VENDOR_SIS 10 +#define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff #if !defined(__PRE_RAM__) @@ -129,8 +129,8 @@ static inline struct cpu_info *cpu_info(void) struct cpu_info *ci; __asm__("andl %%esp,%0; " "orl %2, %0 " - :"=r" (ci) - : "0" (~(CONFIG_STACK_SIZE - 1)), + :"=r" (ci) + : "0" (~(CONFIG_STACK_SIZE - 1)), "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) ); return ci; diff --git a/src/arch/i386/include/arch/io.h b/src/arch/i386/include/arch/io.h index 3a76579fbc..dd8d647380 100644 --- a/src/arch/i386/include/arch/io.h +++ b/src/arch/i386/include/arch/io.h @@ -82,7 +82,7 @@ static inline uint32_t inl(uint16_t port) static inline void outsb(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsb " + "cld ; rep ; outsb " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -91,7 +91,7 @@ static inline void outsb(uint16_t port, const void *addr, unsigned long count) static inline void outsw(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsw " + "cld ; rep ; outsw " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -100,7 +100,7 @@ static inline void outsw(uint16_t port, const void *addr, unsigned long count) static inline void outsl(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsl " + "cld ; rep ; outsl " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -110,7 +110,7 @@ static inline void outsl(uint16_t port, const void *addr, unsigned long count) static inline void insb(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insb " + "cld ; rep ; insb " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -119,7 +119,7 @@ static inline void insb(uint16_t port, void *addr, unsigned long count) static inline void insw(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insw " + "cld ; rep ; insw " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -128,7 +128,7 @@ static inline void insw(uint16_t port, void *addr, unsigned long count) static inline void insl(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insl " + "cld ; rep ; insl " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); diff --git a/src/arch/i386/include/arch/pciconf.h b/src/arch/i386/include/arch/pciconf.h index 09133b5567..a35693519e 100644 --- a/src/arch/i386/include/arch/pciconf.h +++ b/src/arch/i386/include/arch/pciconf.h @@ -1,7 +1,7 @@ #ifndef PCI_CONF_REG_INDEX // These are defined in the PCI spec, and hence are theoretically -// inclusive of ANYTHING that uses a PCI bus. +// inclusive of ANYTHING that uses a PCI bus. #define PCI_CONF_REG_INDEX 0xcf8 #define PCI_CONF_REG_DATA 0xcfc diff --git a/src/arch/i386/include/arch/registers.h b/src/arch/i386/include/arch/registers.h index 63aeec826b..bc1b681339 100644 --- a/src/arch/i386/include/arch/registers.h +++ b/src/arch/i386/include/arch/registers.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h index d69d4541bc..f1466273d8 100644 --- a/src/arch/i386/include/arch/romcc_io.h +++ b/src/arch/i386/include/arch/romcc_io.h @@ -85,7 +85,7 @@ static inline int log2f(int value) typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ -/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, +/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */ @@ -303,7 +303,7 @@ static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); - + for(; dev <=last; dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); diff --git a/src/arch/i386/include/arch/smp/atomic.h b/src/arch/i386/include/arch/smp/atomic.h index 7061461d33..18bbae27cb 100644 --- a/src/arch/i386/include/arch/smp/atomic.h +++ b/src/arch/i386/include/arch/smp/atomic.h @@ -18,29 +18,29 @@ typedef struct { volatile int counter; } atomic_t; /** * atomic_read - read atomic variable * @v: pointer of type atomic_t - * + * * Atomically reads the value of @v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable * @v: pointer of type atomic_t * @i: required value - * + * * Atomically sets the value of @v to @i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_set(v,i) (((v)->counter) = (i)) /** * atomic_inc - increment atomic variable * @v: pointer of type atomic_t - * + * * Atomically increments @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) { __asm__ __volatile__( @@ -52,10 +52,10 @@ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) /** * atomic_dec - decrement atomic variable * @v: pointer of type atomic_t - * + * * Atomically decrements @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ static __inline__ __attribute__((always_inline)) void atomic_dec(atomic_t *v) { __asm__ __volatile__( diff --git a/src/arch/i386/include/arch/smp/mpspec.h b/src/arch/i386/include/arch/smp/mpspec.h index ab29f2a088..1645d3b38f 100644 --- a/src/arch/i386/include/arch/smp/mpspec.h +++ b/src/arch/i386/include/arch/smp/mpspec.h @@ -9,9 +9,9 @@ /* * This tag identifies where the SMP configuration - * information is. + * information is. */ - + #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_') /* @@ -72,7 +72,7 @@ struct mpc_config_processor unsigned char mpc_cpuflag; #define MPC_CPU_ENABLED 1 /* Processor is available */ #define MPC_CPU_BOOTPROCESSOR 2 /* Processor is the BP */ - unsigned long mpc_cpufeature; + unsigned long mpc_cpufeature; #define MPC_CPU_STEPPING_MASK 0x0F #define MPC_CPU_MODEL_MASK 0xF0 #define MPC_CPU_FAMILY_MASK 0xF00 @@ -140,7 +140,7 @@ struct mpc_config_lintsrc unsigned short mpc_irqflag; unsigned char mpc_srcbusid; unsigned char mpc_srcbusirq; - unsigned char mpc_destapic; + unsigned char mpc_destapic; #define MP_APIC_ALL 0xFF unsigned char mpc_destapiclint; } __attribute__((packed)); @@ -211,7 +211,7 @@ struct mp_exten_compatibility_address_space { #define ADDRESS_RANGE_SUBTRACT 1 #define ADDRESS_RANGE_ADD 0 unsigned int mpe_range_list; -#define RANGE_LIST_IO_ISA 0 +#define RANGE_LIST_IO_ISA 0 /* X100 - X3FF * X500 - X7FF * X900 - XBFF @@ -243,7 +243,7 @@ void smp_write_processors(struct mp_config_table *mc); void smp_write_bus(struct mp_config_table *mc, unsigned char id, const char *bustype); void smp_write_ioapic(struct mp_config_table *mc, - unsigned char id, unsigned char ver, + unsigned char id, unsigned char ver, unsigned long apicaddr); void smp_write_intsrc(struct mp_config_table *mc, unsigned char irqtype, unsigned short irqflag, @@ -269,7 +269,7 @@ void smp_write_compatibility_address_space(struct mp_config_table *mc, unsigned int range_list); unsigned char smp_compute_checksum(void *v, int len); void *smp_write_floating_table(unsigned long addr); -void *smp_write_floating_table_physaddr(unsigned long addr, +void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr); unsigned long write_smp_table(unsigned long addr); diff --git a/src/arch/i386/include/bitops.h b/src/arch/i386/include/bitops.h index fae2045b9a..9206465c77 100644 --- a/src/arch/i386/include/bitops.h +++ b/src/arch/i386/include/bitops.h @@ -15,6 +15,6 @@ static inline unsigned long log2(unsigned long x) "1:\n\t" : "=r" (r) : "r" (x)); return r; - + } #endif /* I386_BITOPS_H */ diff --git a/src/arch/i386/include/stdint.h b/src/arch/i386/include/stdint.h index a015a84b2a..b393cc10e0 100644 --- a/src/arch/i386/include/stdint.h +++ b/src/arch/i386/include/stdint.h @@ -9,7 +9,7 @@ /* Exact integral types */ typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef signed char int8_t; typedef unsigned short uint16_t; typedef signed short int16_t; @@ -24,7 +24,7 @@ typedef signed long long int64_t; /* Small types */ typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef signed char int_least8_t; typedef unsigned short uint_least16_t; typedef signed short int_least16_t; @@ -39,7 +39,7 @@ typedef signed long long int_least64_t; /* Fast Types */ typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef signed char int_fast8_t; typedef unsigned int uint_fast16_t; typedef signed int int_fast16_t; @@ -50,7 +50,7 @@ typedef signed int int_fast32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint_fast64_t; typedef signed long long int_fast64_t; -#endif +#endif /* Types for `void *' pointers. */ typedef int intptr_t; diff --git a/src/arch/i386/init/bootblock_prologue.c b/src/arch/i386/init/bootblock_prologue.c index b07aec3524..25da7b769f 100644 --- a/src/arch/i386/init/bootblock_prologue.c +++ b/src/arch/i386/init/bootblock_prologue.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2002 Eric Biederman * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/init/crt0_prologue.inc b/src/arch/i386/init/crt0_prologue.inc index 225a003d8f..8947f20de3 100644 --- a/src/arch/i386/init/crt0_prologue.inc +++ b/src/arch/i386/init/crt0_prologue.inc @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2002 Eric Biederman * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/init/crt0_romcc_epilogue.inc b/src/arch/i386/init/crt0_romcc_epilogue.inc index 73107c913b..3bd1b36992 100644 --- a/src/arch/i386/init/crt0_romcc_epilogue.inc +++ b/src/arch/i386/init/crt0_romcc_epilogue.inc @@ -1,4 +1,4 @@ -/* +/* * Copyright 2002 Eric Biederman * * This file is free software; you can redistribute it and/or @@ -11,7 +11,7 @@ __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -19,7 +19,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/arch/i386/init/ldscript.ld b/src/arch/i386/init/ldscript.ld index e56f644034..149f048638 100644 --- a/src/arch/i386/init/ldscript.ld +++ b/src/arch/i386/init/ldscript.ld @@ -35,6 +35,6 @@ SECTIONS { *(.reset) . = 15 ; BYTE(0x00); - } + } } diff --git a/src/arch/i386/lib/cbfs_and_run.c b/src/arch/i386/lib/cbfs_and_run.c index a6f19e50ee..1b86f56371 100644 --- a/src/arch/i386/lib/cbfs_and_run.c +++ b/src/arch/i386/lib/cbfs_and_run.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/arch/i386/lib/cpu.c b/src/arch/i386/lib/cpu.c index 0e54b9a87d..3732ae296e 100644 --- a/src/arch/i386/lib/cpu.c +++ b/src/arch/i386/lib/cpu.c @@ -43,7 +43,7 @@ static int have_cpuid_p(void) * by the fact that they preserve the flags across the division of 5/2. * PII and PPro exhibit this behavior too, but they have cpuid available. */ - + /* * Perform the Cyrix 5/2 test. A Cyrix won't change * the flags, while other 486 chips will. @@ -68,11 +68,11 @@ static inline int test_cyrix_52div(void) * Detect a NexGen CPU running without BIOS hypercode new enough * to have CPUID. (Thanks to Herbert Oppmann) */ - + static int deep_magic_nexgen_probe(void) { int ret; - + __asm__ __volatile__ ( " movw $0x5555, %%ax\n" " xorw %%dx,%%dx\n" @@ -81,7 +81,7 @@ static int deep_magic_nexgen_probe(void) " movl $0, %%eax\n" " jnz 1f\n" " movl $1, %%eax\n" - "1:\n" + "1:\n" : "=a" (ret) : : "cx", "dx" ); return ret; } @@ -95,7 +95,7 @@ static struct { } x86_vendors[] = { { X86_VENDOR_INTEL, "GenuineIntel", }, { X86_VENDOR_CYRIX, "CyrixInstead", }, - { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, { X86_VENDOR_UMC, "UMC UMC UMC ", }, { X86_VENDOR_NEXGEN, "NexGenDriven", }, { X86_VENDOR_CENTAUR, "CentaurHauls", }, @@ -124,7 +124,7 @@ static const char *cpu_vendor_name(int vendor) const char *name; name = "<invalid cpu vendor>"; if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && - (x86_vendor_name[vendor] != 0)) + (x86_vendor_name[vendor] != 0)) { name = x86_vendor_name[vendor]; } @@ -173,7 +173,7 @@ static void identify_cpu(struct device *cpu) vendor_name[10] = (result.ecx >> 16) & 0xff; vendor_name[11] = (result.ecx >> 24) & 0xff; vendor_name[12] = '\0'; - + /* Intel-defined flags: level 0x00000001 */ if (cpuid_level >= 0x00000001) { cpu->device = cpuid_eax(0x00000001); @@ -200,7 +200,7 @@ static void set_cpu_ops(struct device *cpu) struct cpu_device_id *id; for(id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) { if ((cpu->vendor == id->vendor) && - (cpu->device == id->device)) + (cpu->device == id->device)) { goto found; } @@ -221,7 +221,7 @@ void cpu_initialize(void) struct device *cpu; struct cpu_info *info; struct cpuinfo_x86 c; - + info = cpu_info(); printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); @@ -240,11 +240,11 @@ void cpu_initialize(void) printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask); - + /* Lookup the cpu's operations */ set_cpu_ops(cpu); - if(!cpu->ops) { + if(!cpu->ops) { /* mask out the stepping and try again */ cpu->device -= c.x86_mask; set_cpu_ops(cpu); @@ -252,7 +252,7 @@ void cpu_initialize(void) if(!cpu->ops) die("Unknown cpu"); printk(BIOS_DEBUG, "Using generic cpu ops (good)\n"); } - + /* Initialize the cpu */ if (cpu->ops && cpu->ops->init) { diff --git a/src/arch/i386/lib/exception.c b/src/arch/i386/lib/exception.c index eb1df20e26..20917b6f40 100644 --- a/src/arch/i386/lib/exception.c +++ b/src/arch/i386/lib/exception.c @@ -4,7 +4,7 @@ #if defined(CONFIG_GDB_STUB) && CONFIG_GDB_STUB == 1 /* BUFMAX defines the maximum number of characters in inbound/outbound buffers. - * At least NUM_REGBYTES*2 are needed for register packets + * At least NUM_REGBYTES*2 are needed for register packets */ #define BUFMAX 400 enum regnames { @@ -62,7 +62,7 @@ static uint32_t gdb_stub_registers[NUM_REGS]; #define GDB_SIGSOUND 42 /* Sound completed */ #define GDB_SIGSAK 43 /* Secure attention */ #define GDB_SIGPRIO 44 /* SIGPRIO */ - + #define GDB_SIG33 45 /* Real-time event 33 */ #define GDB_SIG34 46 /* Real-time event 34 */ #define GDB_SIG35 47 /* Real-time event 35 */ @@ -375,7 +375,7 @@ void x86_exception(struct eregs *info) if (info->vector < ARRAY_SIZE(exception_to_signal)) { signo = exception_to_signal[info->vector]; } - + /* reply to the host that an exception has occured */ out_buffer[0] = 'S'; out_buffer[1] = hexchars[(signo>>4) & 0xf]; @@ -412,7 +412,7 @@ void x86_exception(struct eregs *info) case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ ptr = &in_buffer[1]; - if ( parse_ulong(&ptr, &addr) && + if ( parse_ulong(&ptr, &addr) && (*ptr++ == ',') && parse_ulong(&ptr, &length)) { copy_to_hex(out_buffer, (void *)addr, length); @@ -423,7 +423,7 @@ void x86_exception(struct eregs *info) case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */ ptr = &in_buffer[1]; - if ( parse_ulong(&ptr, &addr) && + if ( parse_ulong(&ptr, &addr) && (*(ptr++) == ',') && parse_ulong(&ptr, &length) && (*(ptr++) == ':')) { @@ -475,7 +475,7 @@ void x86_exception(struct eregs *info) put_packet(out_buffer); } #else /* !CONFIG_GDB_STUB */ - printk(BIOS_EMERG, + printk(BIOS_EMERG, "Unexpected Exception: %d @ %02x:%08x - Halting\n" "Code: %d eflags: %08x\n" "eax: %08x ebx: %08x ecx: %08x edx: %08x\n" diff --git a/src/arch/i386/lib/id.inc b/src/arch/i386/lib/id.inc index 9f402f85b0..443dbad38a 100644 --- a/src/arch/i386/lib/id.inc +++ b/src/arch/i386/lib/id.inc @@ -2,9 +2,9 @@ .globl __id_start __id_start: -vendor: +vendor: .asciz CONFIG_MAINBOARD_VENDOR -part: +part: .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ diff --git a/src/arch/i386/lib/ioapic.c b/src/arch/i386/lib/ioapic.c index efc2ac52fc..d6616f5529 100644 --- a/src/arch/i386/lib/ioapic.c +++ b/src/arch/i386/lib/ioapic.c @@ -40,13 +40,13 @@ void clear_ioapic(u32 ioapic_base) u32 low, high; u32 i, ioapic_interrupts; - printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); /* Read the available number of interrupts */ ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 24; - printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); low = DISABLED; high = NONE; @@ -70,15 +70,15 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) u32 low, high; u32 i, ioapic_interrupts; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n", bsp_lapicid); if (ioapic_id) { - printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); + printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); /* Set IOAPIC ID if it has been specified */ - io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | + io_apic_write(ioapic_base, 0x00, + (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | (ioapic_id << 24)); } @@ -86,7 +86,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 24; - printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); // XXX this decision should probably be made elsewhere, and @@ -101,11 +101,11 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) /* For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. */ - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif #ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); #endif diff --git a/src/arch/i386/lib/pci_ops_auto.c b/src/arch/i386/lib/pci_ops_auto.c index 1f144381ee..92eedd30fb 100644 --- a/src/arch/i386/lib/pci_ops_auto.c +++ b/src/arch/i386/lib/pci_ops_auto.c @@ -33,7 +33,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o) vendor = o->read16(&pbus, bus, devfn, PCI_VENDOR_ID); if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) || ((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) || - (vendor == PCI_VENDOR_ID_MOTOROLA))) { + (vendor == PCI_VENDOR_ID_MOTOROLA))) { return 1; } } @@ -54,8 +54,8 @@ static const struct pci_bus_operations *pci_check_direct(void) outb(0x01, 0xCFB); tmp = inl(0xCF8); outl(0x80000000, 0xCF8); - if ((inl(0xCF8) == 0x80000000) && - pci_sanity_check(&pci_cf8_conf1)) + if ((inl(0xCF8) == 0x80000000) && + pci_sanity_check(&pci_cf8_conf1)) { outl(tmp, 0xCF8); printk(BIOS_DEBUG, "PCI: Using configuration type 1\n"); diff --git a/src/arch/i386/lib/printk_init.c b/src/arch/i386/lib/printk_init.c index d3064046f7..f29ba667f1 100644 --- a/src/arch/i386/lib/printk_init.c +++ b/src/arch/i386/lib/printk_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/i386/lib/stages.c b/src/arch/i386/lib/stages.c index 0605abf49b..a6a232a04a 100644 --- a/src/arch/i386/lib/stages.c +++ b/src/arch/i386/lib/stages.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/arch/i386/llshell/console.inc b/src/arch/i386/llshell/console.inc index 394d5c4f68..84f62e3448 100644 --- a/src/arch/i386/llshell/console.inc +++ b/src/arch/i386/llshell/console.inc @@ -149,7 +149,7 @@ jmp console0 jz 11f ; \ __CONSOLE_INLINE_TX_AL ; \ jmp 10b ; \ -11: +11: #define CONSOLE_EMERG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) @@ -234,7 +234,7 @@ jmp console0 #define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) /* uses: esp, ax, dx */ -console_tx_al: +console_tx_al: __CONSOLE_INLINE_TX_AL RETSP @@ -333,7 +333,7 @@ console_tx_string: cmp $0, %al jne 9f RETSP -9: +9: __CONSOLE_INLINE_TX_AL jmp console_tx_string diff --git a/src/arch/i386/llshell/llshell.inc b/src/arch/i386/llshell/llshell.inc index 6f8996717a..a66ac150b5 100644 --- a/src/arch/i386/llshell/llshell.inc +++ b/src/arch/i386/llshell/llshell.inc @@ -27,16 +27,16 @@ jmp llshell_out // Designed to be an interactive shell that operates with zero // system resources. For example at initial boot. -// to use, jump to label "low_level_shell" +// to use, jump to label "low_level_shell" // set %esp to the return address for exiting -#define UART_BASEADDR $0x3f8 +#define UART_BASEADDR $0x3f8 #define resultreg %esi #define subroutinereg %edi #define freqtime $2193 // 1.93 * freq #define timertime $6000 -.equ sys_IOPL, 110 +.equ sys_IOPL, 110 // .data // .text @@ -75,9 +75,9 @@ cmds: \r\nAll values in hex (0x prefixing ok) \ \r\n" -cr: +cr: .string "\r\n" -spaces: +spaces: .string " " // .globl _start @@ -187,7 +187,7 @@ jz wmemw cmp $0x00776d6c,%eax jz wmeml cmp $0x0000646d,%eax -jz dodmem +jz dodmem cmp $0x6d656d74,%eax jz memt // mem test cmp $0x00727374,%eax @@ -195,7 +195,7 @@ jz rst // reset cmp $0x00525354,%eax jz RST cmp $0x62656570,%eax -jz beep +jz beep cmp $0x0000646c,%eax jz dodl // download to mem <loc> <size> cmp $0x006a6d70,%eax @@ -203,7 +203,7 @@ jz jmpto // jump to location (eax holds return addr) cmp $0x62617564,%eax jz baud // change baudrate cmp $0x00696e74,%eax -jz doint // trigger an interrupt +jz doint // trigger an interrupt cmp $0x63616c6c,%eax jz callto // call assumes memory cmp $0x70757368,%eax @@ -270,7 +270,7 @@ processchar: cmp $0x3A,%al jl subnum cmp $0x47,%al -jl subcaps +jl subcaps //sublc: sub $0x57,%al jmp additupn @@ -370,7 +370,7 @@ jmp displaystring doneshow1: dec %cx cmp $0x0,%cx -jz exitdmem +jz exitdmem add $0x04,%ebx jmp dmemloop exitdmem: @@ -517,7 +517,7 @@ movl $int1a, subroutinereg jmp readnibbles int1a: mov resultreg,%eax -// need to lookup int table? +// need to lookup int table? // int %eax jmp readcommand @@ -560,7 +560,7 @@ jmp *subroutinereg displayhexlinear: mov resultreg,%eax -xchg %al,%ah +xchg %al,%ah rol $0x10,%eax xchg %al,%ah mov %eax,resultreg @@ -602,7 +602,7 @@ jmp *subroutinereg displayasciilinear: mov resultreg,%eax -xchg %al,%ah +xchg %al,%ah rol $0x10,%eax xchg %al,%ah mov %eax,resultreg diff --git a/src/arch/i386/llshell/pci.inc b/src/arch/i386/llshell/pci.inc index eb4d3c3845..7cb741008e 100644 --- a/src/arch/i386/llshell/pci.inc +++ b/src/arch/i386/llshell/pci.inc @@ -11,7 +11,7 @@ * * Notes: This routine is optimized for minimal register usage. * And the tricks it does cannot scale beyond writing a single byte. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the data byte @@ -52,7 +52,7 @@ * Effects: writes a single byte to pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -91,7 +91,7 @@ * Effects: writes a single byte to pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -118,7 +118,7 @@ - + /* * Macro: PCI_READ_CONFIG_BYTE * Arguments: %eax address to read from (includes bus, device, function, &offset) @@ -129,7 +129,7 @@ * Effects: reads a single byte from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -165,7 +165,7 @@ * Effects: reads a 2 bytes from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -201,7 +201,7 @@ * Effects: reads 4 bytes from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant diff --git a/src/arch/i386/llshell/ramtest.inc b/src/arch/i386/llshell/ramtest.inc index 910f01608f..c02cf451ec 100644 --- a/src/arch/i386/llshell/ramtest.inc +++ b/src/arch/i386/llshell/ramtest.inc @@ -6,7 +6,7 @@ jmp rt_skip #define RAMTEST 1 -#if RAMTEST +#if RAMTEST .section ".rom.data" rt_test: .string "Testing SDRAM : " @@ -16,7 +16,7 @@ rt_toomany: .string "Too many errors.\r\n" rt_done: .string "Done.\r\n" .previous #endif - + ramtest: #if RAMTEST mov %eax, %esi @@ -41,7 +41,7 @@ ramtest: /* Display address being filled */ /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ - + CONSOLE_INFO_TX_HEX32(%ebx) CONSOLE_INFO_TX_CHAR($'\r') 2: @@ -110,7 +110,7 @@ ramtest: sub $1, %ecx jz 5f jmp 3b -5: +5: CONSOLE_INFO_TX_STRING($rt_toomany) post_code(0xf1) jmp .Lhlt |