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-rw-r--r--src/arch/armv7/ramstage.ld13
-rw-r--r--src/arch/armv7/romstage.ld2
2 files changed, 9 insertions, 6 deletions
diff --git a/src/arch/armv7/ramstage.ld b/src/arch/armv7/ramstage.ld
index 42090f4610..91efe2c4d0 100644
--- a/src/arch/armv7/ramstage.ld
+++ b/src/arch/armv7/ramstage.ld
@@ -1,7 +1,7 @@
/*
* Memory map:
*
- * CONFIG_RAMBASE : text segment
+ * CONFIG_RAMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
@@ -31,7 +31,7 @@ PHDRS
SECTIONS
{
- . = CONFIG_SYS_SDRAM_BASE;
+ . = CONFIG_RAMSTAGE_BASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
@@ -111,9 +111,6 @@ SECTIONS
}
_eheap = .;
- _stack = CONFIG_STACK_BOTTOM;
- _estack = CONFIG_STACK_TOP;
-
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
@@ -121,6 +118,12 @@ SECTIONS
_ram_seg = _text;
_eram_seg = _eheap;
+ /* The stack lives in SRAM in a different location, so keep
+ * it out of ram_seg
+ */
+ _stack = CONFIG_STACK_BOTTOM;
+ _estack = CONFIG_STACK_TOP;
+
/* Discard the sections we don't need/want */
/DISCARD/ : {
diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld
index 0203efb135..0ebcd53bae 100644
--- a/src/arch/armv7/romstage.ld
+++ b/src/arch/armv7/romstage.ld
@@ -1,7 +1,7 @@
/*
* Memory map:
*
- * CONFIG_RAMBASE : text segment
+ * CONFIG_ROMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment