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-rw-r--r--src/arch/armv7/cache.c18
-rw-r--r--src/arch/armv7/include/arch/cache.h11
-rw-r--r--src/arch/armv7/stages.c2
3 files changed, 30 insertions, 1 deletions
diff --git a/src/arch/armv7/cache.c b/src/arch/armv7/cache.c
index 4046451e34..b4a937bf43 100644
--- a/src/arch/armv7/cache.c
+++ b/src/arch/armv7/cache.c
@@ -76,10 +76,12 @@ void icache_invalidate_all(void)
}
enum dcache_op {
+ OP_DCCSW,
OP_DCCISW,
OP_DCISW,
OP_DCCIMVAC,
OP_DCCMVAC,
+ OP_DCIMVAC,
};
/*
@@ -141,6 +143,9 @@ static void dcache_op_set_way(enum dcache_op op)
case OP_DCISW:
dcisw(val);
break;
+ case OP_DCCSW:
+ dccsw(val);
+ break;
default:
break;
}
@@ -174,6 +179,11 @@ static void dcache_foreach(enum dcache_op op)
}
}
+void dcache_clean_all(void)
+{
+ dcache_foreach(OP_DCCSW);
+}
+
void dcache_clean_invalidate_all(void)
{
dcache_foreach(OP_DCCISW);
@@ -220,6 +230,9 @@ static void dcache_op_mva(unsigned long addr,
case OP_DCCMVAC:
dccmvac(line);
break;
+ case OP_DCIMVAC:
+ dcimvac(line);
+ break;
default:
break;
}
@@ -238,6 +251,11 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
dcache_op_mva(addr, len, OP_DCCIMVAC);
}
+void dcache_invalidate_by_mva(unsigned long addr, unsigned long len)
+{
+ dcache_op_mva(addr, len, OP_DCIMVAC);
+}
+
void dcache_mmu_disable(void)
{
uint32_t sctlr;
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index 8a14ff9388..0756f11813 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -170,6 +170,12 @@ static inline void dccmvac(unsigned long mva)
asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
}
+/* data cache clean by set/way */
+static inline void dccsw(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory");
+}
+
/* data cache invalidate by MVA to PoC */
static inline void dcimvac(unsigned long mva)
{
@@ -289,6 +295,11 @@ void dcache_clean_by_mva(unsigned long addr, unsigned long len);
/* dcache clean and invalidate by modified virtual address to PoC */
void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
+/* dcache invalidate by modified virtual address to PoC */
+void dcache_invalidate_by_mva(unsigned long addr, unsigned long len);
+
+void dcache_clean_all(void);
+
/* dcache invalidate all (on current level given by CCSELR) */
void dcache_invalidate_all(void);
diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c
index 0d2072de50..38d1b1928a 100644
--- a/src/arch/armv7/stages.c
+++ b/src/arch/armv7/stages.c
@@ -52,7 +52,7 @@ void stage_exit(void *addr)
/* make sure any code we installed is written to memory. Not all ARM have
* unified caches.
*/
- dcache_clean_invalidate_all();
+ dcache_clean_all();
/* Because most stages copy code to memory, it's a safe and hygienic thing
* to flush the icache here.
*/