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-rw-r--r--src/arch/armv7/lib/cache.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index d65e021623..c7283f14cf 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -111,6 +111,8 @@ static void dcache_op_set_way(enum dcache_op op)
/* FIXME: do we need to use CTR.DminLine here? */
linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4;
+ dsb();
+
/*
* Set/way operations require an interesting bit packing. See section
* B4-35 in the ARMv7 Architecture Reference Manual:
@@ -144,8 +146,7 @@ static void dcache_op_set_way(enum dcache_op op)
}
}
}
-
- dsb();
+ isb();
}
static void dcache_foreach(enum dcache_op op)