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-rw-r--r--src/arch/x86/postcar.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c
index ea05824e6f..b4efc949b4 100644
--- a/src/arch/x86/postcar.c
+++ b/src/arch/x86/postcar.c
@@ -19,6 +19,7 @@
#include <cpu/x86/mtrr.h>
#include <main_decl.h>
#include <program_loading.h>
+#include <timestamp.h>
/*
* Systems without a native coreboot cache-as-ram teardown may implement
@@ -35,6 +36,8 @@ void main(void)
/* Recover cbmem so infrastruture using it is functional. */
cbmem_initialize();
+ timestamp_add_now(TS_START_POSTCAR);
+
display_mtrrs();
/* Load and run ramstage. */