3 files changed, 64 insertions, 42 deletions
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index df08e80444..f8bbf221cf 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -1,5 +1,5 @@
 ramstage-y += printk.c
-ramstage-y += console.c
+ramstage-y += init.c console.c
 ramstage-y += vtxprintf.c
 ramstage-y += vsprintf.c
 ramstage-y += post.c
@@ -9,12 +9,12 @@ smm-$(CONFIG_DEBUG_SMI) += vtxprintf.c printk.c
 smm-$(CONFIG_SMM_TSEG) += die.c
 
 romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c
-romstage-y += console.c
+romstage-$(CONFIG_EARLY_CONSOLE) += init.c console.c
 romstage-y += post.c
 romstage-y += die.c
 
 bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c
-bootblock-y += console.c
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c
 bootblock-y += die.c
 
 ramstage-$(CONFIG_CONSOLE_SERIAL) += uart_console.c
@@ -25,6 +25,6 @@ ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon_console.c
 
 
-$(obj)/console/console.ramstage.o : $(obj)/build.h
-$(obj)/console/console.romstage.o : $(obj)/build.h
-$(obj)/console/console.bootblock.o : $(obj)/build.h
+$(obj)/console/init.ramstage.o : $(obj)/build.h
+$(obj)/console/init.romstage.o : $(obj)/build.h
+$(obj)/console/init.bootblock.o : $(obj)/build.h
diff --git a/src/console/console.c b/src/console/console.c
index 348264d452..1712877801 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -24,30 +24,13 @@
 #include <console/ne2k.h>
 #include <console/spkmodem.h>
 
-#include <build.h>
-#include <arch/hlt.h>
-#include <arch/io.h>
-
-#if CONFIG_EARLY_PCI_BRIDGE
-/* FIXME: ROMCC chokes on PCI headers. */
-#include <device/pci.h>
-#endif
-
 #ifndef __PRE_RAM__
-#include <string.h>
-#include <types.h>
-#include <option.h>
 
 /* initialize the console */
-void console_init(void)
+void console_hw_init(void)
 {
 	struct console_driver *driver;
-	if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS)
-		console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 
-#if CONFIG_EARLY_PCI_BRIDGE
-	pci_early_bridge_init();
-#endif
 	for(driver = console_drivers; driver < econsole_drivers; driver++) {
 		if (!driver->init)
 			continue;
@@ -104,14 +87,8 @@ int console_tst_byte(void)
 
 #else // __PRE_RAM__   ^^^ NOT defined   vvv defined
 
-void console_init(void)
+void console_hw_init(void)
 {
-#if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \
-    !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE
-
-#if CONFIG_EARLY_PCI_BRIDGE
-	pci_early_bridge_init();
-#endif
 #if CONFIG_CONSOLE_SERIAL
 	uart_init();
 #endif
@@ -127,16 +104,5 @@ void console_init(void)
 #if CONFIG_CONSOLE_USB && CONFIG_USBDEBUG_IN_ROMSTAGE && !defined(__BOOT_BLOCK__)
 	usbdebug_init();
 #endif
-
-	static const char console_test[] =
-		"\n\ncoreboot-"
-		COREBOOT_VERSION
-		COREBOOT_EXTRA_VERSION
-		" "
-		COREBOOT_BUILD
-		" starting...\n";
-	print_info(console_test);
-
-#endif /* CONFIG_EARLY_CONSOLE */
 }
 #endif
diff --git a/src/console/init.c b/src/console/init.c
new file mode 100644
index 0000000000..28934e751e
--- /dev/null
+++ b/src/console/init.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <build.h>
+#include <console/console.h>
+#include <console/uart.h>
+#include <option.h>
+
+#if CONFIG_EARLY_PCI_BRIDGE
+/* FIXME: ROMCC chokes on PCI headers. */
+#include <device/pci.h>
+#endif
+
+void console_init(void)
+{
+#if !defined(__PRE_RAM__)
+	if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS)
+		console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
+#endif
+
+#if CONFIG_EARLY_PCI_BRIDGE
+	pci_early_bridge_init();
+#endif
+
+	console_hw_init();
+
+#if defined(__PRE_RAM__)
+	static const char console_test[] =
+		"\n\ncoreboot-"
+		COREBOOT_VERSION
+		COREBOOT_EXTRA_VERSION
+		" "
+		COREBOOT_BUILD
+		" starting...\n";
+
+	print_info(console_test);
+#endif
+}