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-rw-r--r--src/cpu/allwinner/a10/raminit.c6
-rw-r--r--src/cpu/allwinner/a10/uart.c4
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c
index f3b39cb466..bb4003dfcc 100644
--- a/src/cpu/allwinner/a10/raminit.c
+++ b/src/cpu/allwinner/a10/raminit.c
@@ -205,7 +205,7 @@ static int dramc_scan_readpipe(void)
setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
/* check whether data training process has completed */
- while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING) ;
+ while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING);
/* check data training result */
reg32 = read32(&dram->csr);
@@ -408,7 +408,7 @@ unsigned long dramc_init(struct dram_para *para)
udelay(1);
- while (read32(&dram->ccr) & DRAM_CCR_INIT) ;
+ while (read32(&dram->ccr) & DRAM_CCR_INIT);
mctl_enable_dllx(para->tpr3);
@@ -452,7 +452,7 @@ unsigned long dramc_init(struct dram_para *para)
/* reset external DRAM */
setbits_le32(&dram->ccr, DRAM_CCR_INIT);
- while (read32(&dram->ccr) & DRAM_CCR_INIT) ;
+ while (read32(&dram->ccr) & DRAM_CCR_INIT);
/* scan read pipe value */
mctl_itm_enable();
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
index b976d30c61..45dcaed1b2 100644
--- a/src/cpu/allwinner/a10/uart.c
+++ b/src/cpu/allwinner/a10/uart.c
@@ -82,7 +82,7 @@ static int rx_fifo_empty(struct a10_uart *uart)
*/
static u8 a10_uart_rx_blocking(struct a10_uart *uart)
{
- while (rx_fifo_empty(uart)) ;
+ while (rx_fifo_empty(uart));
return read32(&uart->rbr);
}
@@ -94,7 +94,7 @@ static u8 a10_uart_rx_blocking(struct a10_uart *uart)
*/
static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data)
{
- while (tx_fifo_full(uart)) ;
+ while (tx_fifo_full(uart));
return write32(&uart->thr, data);
}