diff options
Diffstat (limited to 'src/cpu/amd/agesa/family12')
| -rw-r--r-- | src/cpu/amd/agesa/family12/fixme.c | 3 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/family12/model_12_init.c | 12 |
2 files changed, 6 insertions, 9 deletions
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index d946e1bb13..084cae8456 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -14,6 +14,7 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/amd/msr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <AGESA.h> #include "amdlib.h" @@ -75,7 +76,7 @@ void amd_initmmio(void) Address MSR register. */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* Enable Non-Post Memory in CPU */ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index c2f3495eca..c81b18ea72 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -15,6 +15,8 @@ #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <device/device.h> #include <string.h> @@ -23,13 +25,7 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/multicore.h> -#include <cpu/amd/amdfam12.h> - -#define MCG_CAP 0x179 -# define MCA_BANKS_MASK 0xff -#define MC0_STATUS 0x401 static void model_12_init(struct device *dev) { @@ -55,12 +51,12 @@ static void model_12_init(struct device *dev) disable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); enable_cache(); |