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-rw-r--r--src/cpu/amd/agesa/Kconfig7
-rw-r--r--src/cpu/amd/agesa/family12/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family12/romstage.c88
-rw-r--r--src/cpu/amd/agesa/family14/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family14/romstage.c108
-rw-r--r--src/cpu/amd/agesa/family15/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family15/romstage.c97
-rw-r--r--src/cpu/amd/agesa/family15rl/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family15rl/romstage.c91
-rw-r--r--src/cpu/amd/agesa/family15tn/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family15tn/romstage.c93
-rw-r--r--src/cpu/amd/agesa/family16kb/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family16kb/romstage.c93
13 files changed, 583 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index ae5e8549df..cd14975031 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -34,6 +34,13 @@ config CPU_AMD_AGESA
if CPU_AMD_AGESA
+config AGESA_LEGACY
+ def_bool n
+
+config AGESA_NO_LEGACY
+ bool
+ default !AGESA_LEGACY
+
config XIP_ROM_SIZE
hex
default 0x100000
diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc
index 578e178505..5673c6b502 100644
--- a/src/cpu/amd/agesa/family12/Makefile.inc
+++ b/src/cpu/amd/agesa/family12/Makefile.inc
@@ -28,6 +28,7 @@
#*****************************************************************************
romstage-y += fixme.c
+romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c
new file mode 100644
index 0000000000..4fb2e685a7
--- /dev/null
+++ b/src/cpu/amd/agesa/family12/romstage.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <commonlib/loglevel.h>
+#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include <cpu/x86/bist.h>
+#include <superio/smsc/kbc1100/kbc1100.h>
+#include <cpu/x86/lapic.h>
+#include "sb_cimx.h"
+#include "SbPlatform.h"
+#include <arch/cpu.h>
+#include "platform_cfg.h"
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ struct sysinfo *cb = NULL;
+ u32 val;
+
+ post_code(0x35);
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ gpioEarlyInit();
+ sb_poweron_init();
+
+ post_code(0x31);
+
+ board_BeforeAgesa(cb);
+
+ post_code(0x32);
+ post_code(0x33);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ // Load MPB
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x36);
+ agesawrapper_amdinitreset();
+
+ post_code(0x37);
+ agesawrapper_amdinitearly();
+
+ post_code(0x38);
+ agesawrapper_amdinitpost();
+
+ post_code(0x39);
+ printk(BIOS_DEBUG, "sb_before_pci_init ");
+ sb_before_pci_init();
+ printk(BIOS_DEBUG, "passed.\n");
+
+ post_code(0x40);
+ agesawrapper_amdinitenv();
+
+ post_code(0x43);
+ copy_and_run();
+}
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index 9b4e76b96f..71d15fbbf6 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c
new file mode 100644
index 0000000000..16f1408a4a
--- /dev/null
+++ b/src/cpu/amd/agesa/family14/romstage.c
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/bist.h>
+
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <commonlib/loglevel.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/car.h>
+#include <sb_cimx.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ struct sysinfo *cb = NULL;
+ u32 val;
+
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ sb_Poweron_Init();
+
+ post_code(0x31);
+
+ board_BeforeAgesa(cb);
+
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+
+ post_code(0x39);
+ agesawrapper_amdinitearly();
+
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+
+ printk(BIOS_INFO, "Normal boot\n");
+
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+
+ post_code(0x42);
+ amd_initenv();
+
+ } else {
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+
+ agesawrapper_amdinitresume();
+
+ post_code(0x61);
+
+ agesawrapper_amds3laterestore();
+
+ post_code(0x62);
+
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+}
+
diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc
index 5742e7afca..d7cdff7a30 100644
--- a/src/cpu/amd/agesa/family15/Makefile.inc
+++ b/src/cpu/amd/agesa/family15/Makefile.inc
@@ -22,6 +22,7 @@ subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm
romstage-y += fixme.c
+romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
new file mode 100644
index 0000000000..fb02b4fbd0
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/romstage.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <lib.h>
+#include <reset.h>
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <arch/stages.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic.h"
+#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include "northbridge/amd/agesa/family10/reset_test.h"
+#include <nb_cimx.h>
+#include <sb_cimx.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ struct sysinfo *cb = NULL;
+ u32 val;
+
+ post_code(0x30);
+ amd_initmmio();
+ post_code(0x31);
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x33);
+ report_bist_failure(bist);
+
+ board_BeforeAgesa(cb);
+ console_init();
+
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x38);
+ /*
+ * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
+ * Disable all Pcie Bridges to work around It.
+ */
+ sr56x0_rd890_disable_pcie_bridge();
+ post_code(0x39);
+ nb_Poweron_Init();
+ post_code(0x3A);
+ sb_Poweron_Init();
+ }
+ post_code(0x3B);
+ agesawrapper_amdinitearly();
+
+ post_code(0x3C);
+
+ nb_Ht_Init();
+ post_code(0x3D);
+ /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
+ distinguish_cpu_resets(0);
+ soft_reset();
+ die("After soft_reset_x - shouldn't see this message!!!\n");
+ }
+
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+ post_code(0x42);
+
+ post_code(0x50);
+ print_debug("Disabling cache as ram ");
+ disable_cache_as_ram();
+ print_debug("done\n");
+
+ post_code(0x51);
+ copy_and_run();
+}
diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc
index 98a7050c21..4fcaff7405 100644
--- a/src/cpu/amd/agesa/family15rl/Makefile.inc
+++ b/src/cpu/amd/agesa/family15rl/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c
new file mode 100644
index 0000000000..e0a434c8f4
--- /dev/null
+++ b/src/cpu/amd/agesa/family15rl/romstage.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/car.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ struct sysinfo *cb = NULL;
+ u32 val;
+
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ board_BeforeAgesa(cb);
+
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+
+ post_code(0x39);
+ agesawrapper_amdinitearly();
+
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+
+ disable_cache_as_ram();
+ } else {
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ agesawrapper_amdinitresume();
+
+ amd_initcpuio();
+ agesawrapper_amds3laterestore();
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+}
+
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index 98a7050c21..4fcaff7405 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c
new file mode 100644
index 0000000000..fbb70adbb3
--- /dev/null
+++ b/src/cpu/amd/agesa/family15tn/romstage.c
@@ -0,0 +1,93 @@
+
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/car.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ struct sysinfo *cb = NULL;
+ u32 val;
+
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+
+ post_code(0x31);
+
+ board_BeforeAgesa(cb);
+
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+
+ post_code(0x39);
+ agesawrapper_amdinitearly();
+
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+
+ disable_cache_as_ram();
+ } else {
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ agesawrapper_amdinitresume();
+
+ amd_initcpuio();
+ agesawrapper_amds3laterestore();
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+}
diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc
index 9367b458a3..31c3ecfabc 100644
--- a/src/cpu/amd/agesa/family16kb/Makefile.inc
+++ b/src/cpu/amd/agesa/family16kb/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c
new file mode 100644
index 0000000000..f1deeb9092
--- /dev/null
+++ b/src/cpu/amd/agesa/family16kb/romstage.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/car.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ struct sysinfo *cb = NULL;
+ u32 val;
+
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+
+ board_BeforeAgesa(cb);
+
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+
+ post_code(0x39);
+ agesawrapper_amdinitearly();
+
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+
+ /* TODO: Disable cache is not ok. */
+ disable_cache_as_ram();
+ } else {
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ agesawrapper_amdinitresume();
+
+ amd_initcpuio();
+ agesawrapper_amds3laterestore();
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+}
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 03:00:09 +0000