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-rw-r--r--src/cpu/amd/agesa/family14/fixme.c19
-rw-r--r--src/cpu/amd/agesa/family15tn/fixme.c19
-rw-r--r--src/cpu/amd/agesa/family16kb/fixme.c19
3 files changed, 0 insertions, 57 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index c9d30396aa..be7c635471 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -61,25 +61,6 @@ void amd_initcpuio(void)
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
-void amd_initmmio(void)
-{
- UINT64 MsrReg;
- AMD_CONFIG_PARAMS StdHeader;
-
- /*
- Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
- Address MSR register.
- */
- MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
- LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
-
- /* Set ROM cache onto WP to decrease post time */
- MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;
- LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
- MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
- LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
-}
-
void amd_initenv(void)
{
AMD_INTERFACE_PARAMS AmdParamStruct;
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index e92aa9a9bf..03c6503300 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -60,22 +60,3 @@ void amd_initcpuio(void)
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
-
-void amd_initmmio(void)
-{
- UINT64 MsrReg;
- AMD_CONFIG_PARAMS StdHeader;
-
- /*
- Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
- Address MSR register.
- */
- MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
- LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
-
- /* Set ROM cache onto WP to decrease post time */
- MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
- MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
-}
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index 73d09956cd..260efc2643 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -60,22 +60,3 @@ void amd_initcpuio(void)
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
-
-void amd_initmmio(void)
-{
- UINT64 MsrReg;
- AMD_CONFIG_PARAMS StdHeader;
-
- /*
- Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
- Address MSR register.
- */
- MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
- LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
-
- /* Set ROM cache onto WP to decrease post time */
- MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
- MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
-}