summaryrefslogtreecommitdiff
path: root/src/cpu/amd/car
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/amd/car')
-rw-r--r--src/cpu/amd/car/disable_cache_as_ram.c23
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c12
2 files changed, 18 insertions, 17 deletions
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index a8ff1cc17a..af5a2e985d 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -33,7 +33,7 @@ static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
}
static inline __attribute__((always_inline))
-void disable_cache_as_ram(uint8_t skip_sharedc_config)
+void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
{
msr_t msr;
uint32_t family;
@@ -45,15 +45,13 @@ void disable_cache_as_ram(uint8_t skip_sharedc_config)
msr.lo = 0;
msr.hi = 0;
wrmsr(MTRR_FIX_4K_C8000, msr);
-#if CONFIG_DCACHE_RAM_SIZE > 0x8000
- wrmsr(MTRR_FIX_4K_C0000, msr);
-#endif
-#if CONFIG_DCACHE_RAM_SIZE > 0x10000
- wrmsr(MTRR_FIX_4K_D0000, msr);
-#endif
-#if CONFIG_DCACHE_RAM_SIZE > 0x18000
- wrmsr(MTRR_FIX_4K_D8000, msr);
-#endif
+ if (CONFIG_DCACHE_RAM_SIZE > 0x8000)
+ wrmsr(MTRR_FIX_4K_C0000, msr);
+ if (CONFIG_DCACHE_RAM_SIZE > 0x10000)
+ wrmsr(MTRR_FIX_4K_D0000, msr);
+ if (CONFIG_DCACHE_RAM_SIZE > 0x18000)
+ wrmsr(MTRR_FIX_4K_D8000, msr);
+
/* disable fixed mtrr from now on,
* it will be enabled by ramstage again
*/
@@ -110,8 +108,3 @@ void disable_cache_as_ram(uint8_t skip_sharedc_config)
}
#endif
}
-
-static void disable_cache_as_ram_bsp(void)
-{
- disable_cache_as_ram(0);
-}
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 064222a454..c647254c70 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -26,9 +26,17 @@
#include <cpu/amd/msr.h>
#include <arch/acpi.h>
#include <romstage_handoff.h>
-#include "cbmem.h"
+#include <cbmem.h>
+
#include "cpu/amd/car/disable_cache_as_ram.c"
+// For set_sysinfo_in_ram()
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8)
+#include "northbridge/amd/amdk8/raminit.h"
+#else
+#include "northbridge/amd/amdfam10/raminit.h"
+#endif
+
#if CONFIG_RAMTOP <= 0x100000
#error "You need to set CONFIG_RAMTOP greater than 1M"
#endif
@@ -171,7 +179,7 @@ void post_cache_as_ram(void)
void cache_as_ram_new_stack(void)
{
print_car_debug("Disabling cache as RAM now\n");
- disable_cache_as_ram_bsp();
+ disable_cache_as_ram_real(0); // inline
disable_cache();
/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */